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Assertion-Based Verification
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC System Design, Verification, and Testing, 2018
Functional verification is a process of confirming that the intent of the design was preserved during its implementation. Hence, this process requires two key components: a specification of design intent and a design implementation. Yet historically, describing design intent in a fashion useful to the verification process has been problematic. For example, typical forms of specification are based on natural languages, which certainly do not lend themselves to any form of automation during the verification process. Furthermore, ambiguities in the specification often lead to misinterpretation in the design and verification environments. The problem is compounded when a verification environment cannot be shared across multiple verification processes (that is, the lack of interoperability between the specification and the various verification environments for simulation, acceleration, emulation, or formal verification).
Assertion-Based Verification
Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
Functional verification is a process of confirming that the intent of the design was preserved during its implementation. Hence, this process requires two key components: a specification of design intent and a design implementation. Yet historically, describing design intent in a fashion useful to the verification process has been problematic. For example, typical forms of specification are based on natural languages, which certainly do not lend themselves to any form of automation during the verification process. Furthermore, ambiguities in the specification often lead to misinterpretation in the design and verification environments. The problem is compounded when a verification environment cannot be shared across multiple verification processes (i.e., the lack of interoperability between the specification and the various verification environments for simulation, acceleration, emulation, or formal verification).
A product-process-resource based formal modelling framework for customized manufacturing in cyber-physical production systems
Published in International Journal of Computer Integrated Manufacturing, 2022
Ge Wang, Di Li, Yuqing Tu, Chunhua Zhang, Fang Li, Shiyong Wang
In the formal verification, functional verification can be regarded as the calculation result of the formal model conforming to the expected result, in order for the expected state to be reachable or deadlock-free. Table 1 shows the features incorporated in the proposed method.