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Equivalence Checking
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
Andreas Kuehlmann, Fabio Somenzi
When trying to prove combinational circuits equivalent, reasoning on the circuits themselves allows one to detect structurally identical subcircuits, which can be merged to simplify the proof of equivalence of the remaining parts. This approach can be extended in two important ways. First, one can use a semi-canonical circuit representation to increase the chances that equivalent circuits will have the same structure. One example of this semicanonical representation is the and-inverter graph (AIG) [14], in which every node of the circuit is an AND gate whose inputs may be inverted. One can quickly identify isomorphic subcircuits in an AIG by hashing the gates. The second extension to structural comparison consists of computing signatures for the nodes of a circuit so that nodes with different signatures are known not to be equivalent. The few nodes with identical signatures can be subjected to further, more expensive, analysis to establish whether they are equivalent. Signature computation is usually based on simulation [25], while the more expensive analysis techniques can be based on either BDDs or CNF SAT.
Cost-efficient method for inverter reduction and proper placement in quantum-dot cellular automata
Published in International Journal of Electronics, 2022
Amit Kumar Pramanik, Jayanta Pal, Kumar Mohit, Mrinal Goswami, Bibhash Sen
An approach was illustrated in (Wang et al., 2013) to obtain minimal majority expressions for various functions (up to four variables). This approach plays an essential role in reducing gate count and gate level. A look-up table for majority expression was developed in (Wang et al., 2015), to synthesise the four or lesser variables’ boolean functions. This technique aimed to decrease the count of the majority gate and level in synthesising boolean functions. A method based on the majority inverter graph was presented in (Peng et al., 2021) to synthesize the QCA circuits. In implementing QCA circuits, the target of the above minimisation methods is to reduce the majority gate. Although still no such minimization methods are reported for inverter reduction in the QCA circuit.