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Audio Codecs
Published in Francis F. Li, Trevor J. Cox, Digital Signal Processing in Audio and Acoustical Engineering, 2019
Nowadays, sigma-delta modulation based ADCs and DACs are used prevalently in audio and acoustic systems as alternative converters to traditional high-precision ADCs such as the consecutive approximation ones. A low-precision ADC with very few bits working at much higher than the Nyquist sampling rate can achieve the same precision as high bit depth ADCs. This is known as oversampling as noise shaping techniques. For example, commonly used ADC and DAC in today's audio systems and sound cards typically use 1-bit ADCs with oversampling and noise shaping to achieve 16 or even higher equivalent bit depths. Lower-bit, especially 1-bit, ADC offers a cost-effective solution for high-definition audio and video signals. In the meantime, the oversampling also mitigates the design constraints and costs of analogue anti-aliasing filters. When the sampling rate is sufficiently high, the anti-aliasing filtering stage might even be omitted completely. In 1-bit data conversion, an analogue signal is converted or encoded into a bit stream. Such bit streams form a new encoding method and can be stored on large capacity media, which is how super audio CD (SACD) works.
Delta-Sigma Data Converters
Published in Tertulien Ndjountche, CMOS Analog Integrated Circuits, 2017
The block diagram of a delta-sigma DAC is depicted in Figure 12.64. It comprises a digital interpolation filter, a digital delta-sigma modulator, a low-resolution DAC, and an analog lowpass filter. The input signal is assumed to be a stream of digital words with N bits. It is processed by a digital interpolation filter, which raises the data rate to OSR ⋅ fs, where OSR is the oversampling ratio and fs is the sampling rate, by inserting OSR − 1 equidistant zerovalued samples between two consecutive samples of the input sequence. The oversampled signal is then supplied to a digital modulator or noise shaper, which reduces the word-length, generally to 1 bit. An analog version of the modulator output is provided by the reconstruction stage, which includes a low-resolution DAC and a lowpass (smoothing) filter.
Vibration Measurement
Published in Neil J. Mansfield, Human Response to Vibration, 2004
The signal is repeatedly “sampled” and each sample is converted to a binary number by an analog-to-digital converter (ADC). The length of the binary number is prescribed by the number of bits. For example, a single-bit number can be either 0 or 1; a 2-bit number can be 00, 01, 10, or 11. Each additional bit doubles the number of possible values or “states” that the ADC can assign. For the single-bit system, there are 21 possible states (i.e., 2); for the 2-bit system, there are 22 possible states (i.e., 4). Similarly, a 12-bit system can measure a possible 212 (i.e., 4096) states, a 16-bit system can measure a possible 216 (i.e., 65,536) states, and a 24-bit system can measure a possible 224 states (i.e., over 16 million possible values). In principle, the ADC selects the state that is closest to the value of the measured voltage. Figure 5.2 illustrates how the sampled signal might be measured for 1-, 2-, and 3-bit converters. The sampled signal for the 1-bit ADC bears little resemblance to the original signal; as the characteristics of the ADC improves, the fidelity of the sampled signal improves.
Regular Clocking based Emerging Technique in QCA Targeting Low Power Nano Circuit
Published in International Journal of Electronics, 2022
Jayanta Pal, Amit Kumar Pramanik, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen
SR (Set-Reset) latch is important in controlling the applications, where set or reset the data bit is required (Mano, 2017). An SR latch is an asynchronous device works differently for the given control signals depending on the S & R inputs which can be defined as . 1-bit of data is stored in it as long as it is activated. The SR Latch sequential circuit designed in the proposed clocking scheme and the QCA layout can be found in Figure 12(a). The introduced SR latch design in this paper consisting 23 cells, utilising 0.04 area and only one latency (four clock zones). The simulated result, as shown in Figure 12(b) shows, the sequence of order of output against the inputs as hold (R = 0, S = 0), reset (R = 1, S = 0), set (R = 0, S = 1) and hold (R = 1, S = 1). Therefore, for the given input vectors S = 0000 1111; R = 0101 0101 the output vector Q generated as X011 1011. ’X’ in the output vector depends on the previously generated output.
Reversible Data Hiding in Encrypted Images Based on Hybrid Cryptosystem
Published in IETE Technical Review, 2021
For blocks , following the work [15], each block can be embedded up to 1 bit, and separated into two equal-sized sets and according to the data hiding key. If the to-be-embedded bit is “0”, flip the 3 LSBs in and generate the marked encrypted bits. Otherwise, flip the 3 LSBs in and generate the marked encrypted bits. Then, the marked encrypted blocks are obtained and collected with marked encrypted blocks to form a marked encrypted image.
A unified reconfigurable CORDIC processor for floating-point arithmetic
Published in International Journal of Electronics, 2020
Linlin Fang, Bingyi Li, Yizhuang Xie, He Chen, Long Pang
The mantissa is shifted according to the result of E minus 127, and it is converted into fixed-point form of 1-bit sign, 1-bit integer and 23-bit decimal part. In this module, the fixed-point numbers are expressed as DX, DY and DZ. Then, we use the method of mathematical transformation to map the data of entire circumference to the range of which can be covered by CORDIC algorithm. We divide the entire circumference into five domains and encode it by S2&S1&S0. Through the mapping relations in Table 3, the input phase or vector in interval B, C, D or E can be transformed into domain A. NX, NY, NZ are the output values after the operation.