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Design Closure
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
Soft error upsets are recoverable events caused by high-energy charged particles which either originate from outer space or from nearby radioactive materials. The carriers induced by the charged particle as it travels through the silicon substrate of the chip can disrupt the logic state of sensitive storage elements. The amount of charge required to upset a logic gate is dependent on its critical charge or Qcrit. As device structures shrink, the amount of charge required to cause logic upset is decreasing. SEU is currently a concern for memory arrays and dynamic logic, though some projections show that standard logic latch structures might also soon be susceptible to particle- induced soft errors. SEU is best addressed at the architecture level through the addition of logical redundancy or error-correction logic, which is not a design closure step per se.
Soft-Error Resilient Circuit Design
Published in Tomasz Wojcicki, Krzysztof Iniewski, VLSI: Circuits for Emerging Applications, 2017
Chia-Hsiang Chen, Phil Knag, Zhengya Zhang
Soft errors are nondestructive, nonpermanent, and nonrecurring errors. They were first observed in dynamic random-access memory due to α particles emitted by lead-based package in the 1970s [1]. Neutrons in cosmic rays were found as another important source of soft errors [2–4]. These energetic particles travel through the silicon substrate and create minority carriers. When enough minority carriers are collected by a nearby transistor’s drain diffusion node, it will result in a potential disruption of the stored 0 or 1 state, or a voltage transient, resulting in soft errors [5–7]. Soft errors belong to the broader class of single-event effects, defined as any measurable or observable change in state of performance of a device resulting from a single energetic particle strike [8]. Soft errors include single-event upset (SEU), that is, a soft error caused by a single energetic particle strike [5,6], and single-event transient (SET), that is, a momentary voltage spike at a circuit node caused by a single energy particle strike [9].
Effects of Terrestrial Radiation on Integrated Circuits
Published in Robert Doering, Yoshio Nishi, Handbook of Semiconductor Manufacturing Technology, 2017
Ionization collected from terrestrial radiation events can cause data errors leading to failures in electronic devices. At terrestrial altitudes three mechanisms are responsible for soft errors: the reaction of high-energy cosmic neutrons with silicon and other device materials, alpha particles emitted from trace radioactive impurities in the device materials, and the reaction of low-energy cosmic neutrons with high concentrations of 10B in the device. The soft error sensitivity as a function of technology scaling for various memory and logic devices used to create advanced commercial microelectronic components revealed that while the soft error susceptibility of DRAM in a system is relatively unchanged by scaling, SRAM, and peripheral logic system susceptibility to soft errors is increasing rapidly with each new technology node. The efficacy of various methods to mitigate soft errors has been reviewed with the insight that memory system soft error reliability is best addressed by employing EDAC techniques, while sequential logic robustness can best be improved by design hardening. In closing, the reader is reminded that unlike other hard reliability mechanisms, where a single failure criteria can generally be applied to all products built with a particular technology, the actual customer impact of soft errors is extremely application-dependent. For single-user commercial applications, soft errors are typically not a concern, while for larger (multi-chip) or high-reliability applications, full error correction and/or redundancy techniques are mandatory.
Electron inducing soft errors in 28 nm system-on-Chip
Published in Radiation Effects and Defects in Solids, 2020
Weitao Yang, Yonghong Li, Weidong Zhang, Yaxin Guo, Haoyu Zhao, Jianan Wei, Yang Li, Chaohui He, Kesheng Chen, Gang Guo, Boyang Du, Sterpone Luca
A soft error occurs when a radiation event causes enough charge disturbance to reverse or flip the data state of a memory cell, it is ‘soft’ because the electronic device is not permanently damaged by the radiation (13–14). As predicted, once the critical charge of the advanced electronic devices is less than 0.1 fC, energetic electrons even play the dominating role on electronic devices’ soft error rates (3). This highlights the electron effects really cannot be ignored for the future near-Earth or Jovian missions. In (4), by electron beam irradiation, the 28 nm static random access memory (SRAM) was considered hard to total dose and sensitive to soft errors.
CASH: correlation-aware scheduling to mitigate soft error impact on heterogeneous multicores
Published in Connection Science, 2021
Jiajia Jiao, Libao Wang, Yanxiang Li, Dezhi Han, Min Yao, Kuan-Ching Li, Hai Jiang
To mitigate the soft error impacts on processors, various protection schemes have been proposed. Unlike the hardware approaches to mitigate the soft error-sensitive microarchitecture components like the register file (Tan et al., 2015), cache (Khoshavi et al., 2016), issue queue (Tang & Huang, 2016), ALUs (Hasan & Tangellapalli, 2017), memory (Guo et al., 2015) and others, the reliability-aware scheduling for soft error alleviation is still a new field in heterogeneous multicore. We have developed CASH to approach that challenge.
The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology
Published in Radiation Effects and Defects in Solids, 2018
N. S. Yusop, A. N. Nordin, M. Azim Khairi, N. F. Hasbullah
Such faults are referred to as soft error as they did not cause permanent damage to a device (2). The susceptibility of soft error towards the memory cell and the logic circuit increases as technology scale down to nanometre. Consequently, this increment reduces the noise margin and lowers the signal charge due to the lower voltage supply and smaller node capacitance (1).