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Analog-to-Digital Conversion
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
James C. Anderson, Helen H. Kim
The SFDR is a frequency-domain measurement that determines the minimum signal level that can be distinguished from spurious components, and includes all spurious components over the full Nyquist band regardless of their origin (IEEE 2000; Kester and Bryant 2000). SFDR for a given ADC typically decreases as the sampling rate increases. SFDR values may be referenced either to a carrier level (dBc) or to an input level that is nearly full-scale (dBFS), as shown in Figure 7-4. SFDR is often caused by the worst of second or third harmonic distortion. Since it is one of the main factors limiting the effectiveness of digital signal processing techniques for signal enhancement, a number of technologies have been developed to improve SFDR performance (Batruni 2006; Lundin, Skoglund, and Handel 2005; Raz 2003; Velazquez and Velazquez 2002; White, Rica, and Massie 2003).
Data Converter Basics
Published in Bang-Sup Song, Micro CMOS Design, 2017
SNDR is always lower than SNR. Another definition widely used in radio frequency (RF) receiver systems is the spurious-free dynamic range (SFDR), which is defined as the ratio of the carrier to the highest spurious tone.
Antennae
Published in David A. Cardwell, David C. Larbalestier, Aleksander I. Braginski, Handbook of Superconductivity, 2022
Heinz J. Chaloupka, Victor K. Kornev
Recently developed broadband, active, ESAs [32–35] use SQAs [33–38] capable of providing a high (up to 90 to 100 dB) spurious-free dynamic range (SFDR), the ratio of the highest output signal amplitude to the strongest spurious component (among the rms value of noise and the nonlinear distortions). Their application is associated primarily with broadband superconductor receivers with direct signal digitizing and following digital extraction of sub-bands with programmable band location and bandwidth [39–47], although other applications are possible, particularly with further progress in HTS Josephson junction circuit technology (see the progress achieved in [48–55]). Figure H2.3.8 shows schematically a broadband receiving system with one single analog-to-digital converter (ADC). Recent advantages in technology of the low-Tc superconductor ADCs capable of providing outstanding linearity and dynamic range jointly allowing SFDR of up to 90 to 100 dB [56–60] make the realization of such receivers feasible. However, the inferior linearity and dynamic range of a conventional antenna and a low-noise amplifier as compared to those of the ADC can essentially constrain the overall system performance. To overcome this limitation, a broadband high-sensitivity SQA-based active ESA can be used. The devices are composed of SQUID-type circuits, which can work correctly at signal frequencies ranging from dc to extremely high frequencies F (tens of GHz), limited only by the characteristic Josephson oscillation frequency Fc=Vc/Φ0
An improved Random Swapping Thermometer Coding (RSTC) Dynamic Element Matching (DEM) method
Published in International Journal of Electronics Letters, 2021
Mohammadreza Armuti, Mehdi Bandali, Omid Hashemipour
An 8-bit Current Steering Thermometer coded DAC has been designed in 180nm CMOS technology with the supply voltage of 1.8 V. The DAC has been simulated at the sample rate of 200MS/s. In order to show the drawback of ”RSTC with restricted jumping technique” method and the advantage of the proposed DEM method, a sinusoidal with 2LSB lower amplitude than the full-scale signal is used as the input. The error profile of Current Sources is the random uncorrelated mismatches with a Gaussian-independent distribution and 3.3% relative standard deviation of the weight of the unit Current Source. The SFDR is calculated by Fast Fourier Transform (FFT) analysis on samples. Figure 12 shows the SFDR diagram of the 8-bit DAC in the Nyquist range while employing ”RSTC with restricted jumping technique” method and the proposed DEM method. In this simulation, the non-linearity of circuit elements (for example, transistors) affects the SFDR and consequently, the SFDR reduces in comparison to the behavioural simulation. It can be noted that employing the proposed method results in much higher SFDR in low frequencies than employing ”RSTC with restricted jumping technique” method.
FPGA Realisation of n-QAM Digital Modulators
Published in IETE Technical Review, 2019
J. A. Galaviz-Aguilar, J. C. Nuñez-Perez, F. J. Perez-Pinal, E. Tlelo-Cuautle
The modulator design is verified in Modelsim-Altera by means of the test bench-based VHDL, PLL [17], and NCO libraries. This simulation provides a verification of quadrature signals generation. The steps resolution for one cycle in the waveforms is given by Equation (8) and shown by Figure 8. Assuming 14-bit output resolution, Figure 9 verifies the power spectral of a complex signal at 4 MHz. SFDR is measured from the fundamental frequency and the most prominent amplitude in the output spurious signals. SFDR = 80 dB/Hz, showing a larger separation accomplished by the dithering improvement. The proposed design methodology is shown in Figure 10. Figure 11 shows the simulation of 8-, 16-, and 64-QAM modulators.