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Reconfigurable Communication Infrastructure in the FCR
Published in Lev Kirischian, Reconfigurable Computing Systems Engineering, 2017
Since DDR LVDS communication bus requires much less of expensive PCB space, the second approach is often considered as more cost efficient. However, it assumes existing on-chip parallel to serial conversion mechanism (circuit). This mechanism is called SerDes and allows conversion of parallel data word to the series of bits and vice-versa. This is the reason why most FPGA vendors have started to include hardware cores for multigigabit SerDes in their recent FPGA devices (e.g., Xilinx 7 Series FPGA [17] or ALTERA Stratix FPGA [18]). It is necessary to mention that utilization of the aforementioned SerDes units will increase the cost of the associated boards due to (1) additional power and ground layers, (2) special radio frequency (RF) signal layer(s) layout on the multilayer PCB, (3) SI simulation prior to PCB manufacturing, and (4) postmanufacturing test of actual bandwidth using relatively expensive instruments. Thus, there are certain trade-offs associated with utilization of parallel versus serial methods in designing on-board high-bandwidth buses. Quite often, the parallel synchronous approach is used for relatively short (up to 100 mm) buses using single-ended LVTTL lines. For longer on-board lines and frequencies exceeding 200 MHz, the LVDS-based custom buses are more cost efficient. For interboard communication, utilization of multigigabit SerDes cores became a “de facto” standard solution in recent years. SerDes devices can be built-in to the FPGAs or can be separate stand-alone devices for interboard communication. The optical (light emitting diode [LED] or laser-based) or RF coaxial cables are the usual communication media for SerDes devices. In both cases, the bandwidth can exceed 10 Gb/s. However, utilization of optical cables is preferable in many cases specifically when electromagnetic interference could be an issue.
Main Architectures and Hardware Resources of FPGAs
Published in Juan José Rodríguez Andina, Eduardo de la Torre Arnanz, María Dolores Valdés Peña, FPGAs, 2017
Juan José Rodríguez Andina, Eduardo de la Torre Arnanz, María Dolores Valdés Peña
SerDes blocks are serial–parallel (input deserializer) and parallel–serial (output serializer) conversion circuits to interface digital systems with serial communication links. They significantly ease the implementation of systems with high data transfer rate requirements, such as in video applications, high-speed communications, high-speed data acquisition, and serial memory access.
Adaptive timing correction technique for pulse-amplitude and pulse-position modulation interface
Published in International Journal of Electronics, 2019
Waleed Madany, Mostafa Rashdan, El-Sayed Hasaneen
In SerDes links, a high-speed input clock signal that is generated using a high precise phase-locked loop (PLL) circuit is used to multiplex the parallel input bits into a high-speed signal. Clock and data recovery (CDR) circuit is used at the receiver to separate the clock signal and data signal from the received signal. Unfortunately, in SerDes links, the operating frequency of the input clock signal is proportional to the number of the transmitted data bits. So, increasing the data rate complicates the design of the PLL circuit and increases its power consumption (Sai, Yamaji, & Itakura, 2011). Also, a complicated pre-emphasis and equalization techniques are required to compensate for the effect of the transmission channel on the high-speed transmitted signal (Higashi et al., 2004).