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Timing and Clocking
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
John George Maneatis, Fabian Klass, Cyrus (Morteza) Afghahi
After sufficient differential voltage is developed between V1 and V2, the SenSel signal is activated. Initially, only two input N transistors, N1 and N2, are in saturation and two loading P transistors are off. This is a favorable case because N transistors normally have better matching characteristics than P transistors. Two cross-coupled N transistors increase the differential voltages further. Both V1 and V2 drop below pre-charge Vcc voltage. When V1 or V2 are below Vcc − Vtp, the P transistors further increase the positive feedback and restore a full Vcc on the side that is supposed to be a logic “1”. To make the initial part of the operation longer, one may use a dual slope scheme or/and clock the Vcc connection, Fig. 7.86c. In the dual slope scheme first the weaker tail transistor is activated. This will cause the V1 and V2 to sink slowly. After a short delay the strong tail transistor is turned on by SenSel. In the clocked Vcc connection the ΦL is delayed with respect to SenSel. In some design the Bit and Bit# are not disconnected from the sense amplifier during sensing. This results in slower response and increased power consumption. Bit and Bit# can be disconnected by a column select transistors to increase speed and reduce power consumption.
Diagnostics
Published in Tom Denton, Electric and Hybrid Vehicles, 2020
The waveform shown as Figure 9.18, is from a car that is working normally. Figure 9.19 is a car with a shorted DC link capacitor. Voltage is shown in blue and current shown in red. In the good example, the voltage builds quickly, and current tails off quickly. There is then a second current surge as the main relay takes over from the pre-charge relay. The one with a fault shows no voltage, and as you can see, the scope proves the presence of a short by the fact current flows. If the fault were an open circuit, there would be no current flow. If we disconnect the inverter and test the rest of the system using the insulation tester and it proves to be ok, this means the fault must be in the inverter.
Circuit Protection, Vacuum Circuit Breakers, and Reclosers
Published in Paul G. Slade, The Vacuum Interrupter, 2020
The current counterpulse scheme has been successfully employed for switching the dc current in the Ohmic-heating coil for fusion experiments in the U.S.A. [264,274,275], Europe [273,276], and Japan [277]. The design of a successful “Ohmic-heating interrupter” that my team at Westinghouse helped develop [273] is shown in Figure 6.111. Typical parameters for this interrupter are given in Table 6.25. A dc current of 24kA initially flows through the Ohmic-heating coil (OH) and the closed vacuum interrupters. The plasma striking voltage is created by opening the two vacuum switches and by discharging the counterpulse current from the parallel capacitor. This diverts the current to the energy dissipation resistor R. The insertion of this resistor results in a rapid rate of decay of the current, which produces the striking voltage [263,274,275]. The current and voltage characteristics are shown in Figure 6.112. A current (io) is established in the Ohmic-heating coils. The vacuum interrupters are then opened to their designed contact gap and a high current, diffuse vacuum arc is established. The AMF is supplied by the circuit current opening through field coils external to the vacuum interrupters. The counter pulse from the charged capacitors is only initiated once the high current vacuum arc is in the fully diffuse mode. As the counter pulse timing has to be operated at a very precise time, an ignitron initiated the counter pulse current. During the counter pulse and interruption period, the current in the vacuum interrupters is forced to zero with a high rate of current decrease (di/dtm = 0.15 kA/μs). The inductance of the series saturable reactor shown between the vacuum interrupters becomes large at low currents and the (di/dt0 = 0.03 kA/μs) through the vacuum interrupters slows down just before the current zero. The slower rate of current decrease gives cathode spots from the diffuse vacuum arc a longer time to extinguish. This assists the recovery of the vacuum interrupters when the TRV is imposed across the open contacts once the current goes to zero. At current zero, when the vacuum arc extinguishes, a part of the pre-charge voltage remains as a residual voltage on the counterpulse capacitor C. After interruption, it is discharged in the OH coil. The vacuum interrupters see this voltage as the small negative voltage pulse (Uo). Later, C is charged by the stored energy in the OH coil and this is the TRV (dUR/dt to UR(peak)) seen across the open contacts of the vacuum interrupters.
Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies
Published in IETE Journal of Research, 2023
Divya Sharma, Amrita Rai, Sunita Debbarma, Om Prakash, Mukesh Kumar Ojha, Vijay Nath
Efficient Charge Recovery Logic (ECRL): Efficient charge recovery logic is formed by using two cross-coupled PMOS transistors and two NMOS structures [19]. It uses AC power supply for recovering and reusing the supplied energy. In this technique, the constant load capacitance is always generated by the power clock which does not depend on input signal [20]. This methodology eliminates the pre-charge diode and evaluates at the same time [21]. Hence, it dissipates less energy as compared to the adiabatic systems and full output swing can be obtained both in pre-charge and recovery phase 2 [22]. The circuit also suffers from adiabatic loss due to the threshold voltage of PMOS transistors both in pre-charge and recovery phase due to which it fails to give output for full swing [23,24]. The effectiveness of this approach is shown by the design of inverter and 4:1 multiplexer in the paper [2,25].
Speed enhancement techniques for Clock-Delayed Dual Keeper Domino logic style
Published in International Journal of Electronics, 2020
A. Anita Angeline, V.S. Kanchana Bhaaskaran
Here, Cdyn is the total capacitance at dynamic node and it depends on , the drain capacitance of the pre-charge transistor , the source diffusion capacitance exerted by PDN and CK or CK1, the effective keeper transistor capacitance and the sum of effective gate capacitances of static inverter and which is contributed by the NMOS and PMOS transistor’s gate capacitances namely and . The capacitive load impact due to the capacitances and the PDN is identical in both conventional domino logic and CDDK domino logic. Hence, achieving during the initial evaluation phase greatly reduces the net dynamic node capacitance Cdyn. This makes the dynamic node to be pre-charged in a faster manner with reduced time delay TD and stated as
Optimisation of SRAM cell in 7-nm node by response surface method
Published in International Journal of Electronics, 2022
Ding Yan-Yan, Guangjun Zhang, Yanfeng Jiang
Being different from the data writing on 6-T SRAM cell, the reading operation has the extra operation that the bit line needs to be pre-charged (Kabir & Chan, 2015). In Figure 12, the data are obtained when the power supply voltage is 0.9 V. It can be seen in Figure 12(e) that when the pre-charged voltage drops from VDD, the read noise margin is almost kept constant at the beginning. After the pre-charge, the voltage drops to 60% of the power supply voltage. The noise margin is decreased significantly as the pre-charge voltage drops. Therefore, in the circuit design, the pre-charge voltage should exceed 60% of the power supply voltage to ensure the balance between the noise tolerance and the power consumption.