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Published in Richard C. Dorf, Circuits, Signals, and Speech and Image Processing, 2018
J. Gregory Rollins, Sina Balkir, Peter Bendix
Unfortunately, computer-aided simulation has its own problems: Real circuits are distributed systems, not the “lumped element models” which are assumed by simulators. Real circuits, therefore, have resistive, capacitive, and inductive parasitic elements present besides the intended components. In high-speed circuits these parasitic elements are often the dominant performance-limiting elements in the circuit, and must be painstakingly modeled. In addition, this modeling effort requires accompanying parasitic extractor software for the circuit under development. The results of parasitic extraction then need to be back-annotated to the original design for further verification and/or fine-tuning, rendering the overall design flow complicated.Suitable predefined numerical models have not yet been developed for certain types of devices or electrical phenomena. The software user may be required, therefore, to create his or her own models out of other models which are available in the simulator. (An example is the solid-state thyristor which may be created from a NPN and PNP bipolar transistor.)The numerical methods used may place constraints on the form of the model equations used.
Computer-Aided Analysis
Published in Wai-Kai Chen, Computer Aided Design and Design Automation, 2018
J. Gregory Rollins, Peter Bendix
Unfortunately, computer-aided simulation has its own problems:Real circuits are distributed systems, not the “lumped elements models” which are assumed by simulators. Real circuits, therefore, have resistive, capacitive, and inductive parasitic elements present besides the intended components. In high-speed circuits these parasitic elements are often the dominant performance-limiting elements in the circuit, and must be painstakingly modeled.Suitable predefined numerical modes have not yet been developed for certain types of devices or electrical phenomena. The software user may be required, therefore, to create his or her own models which are available in the simulator. (An example is the solid-state thyristor which may be created from a NPN and PNP bipolar transistor.)Numerical methods used may place constraints on the form of the model equations used.
SOI Technologies for RF and Millimeter-Wave Applications
Published in Simon Deleonibus, Convergence of More Moore, More Than Moore, and Beyond Moore, 2021
Martin Rack, Jean-Pierre Raskin
At high frequency, the accurate modeling of parasitic elements is crucial to IC design. This is especially true in advanced nodes that are usually expensive, and it is, therefore, a cost requirement to minimize the number of fabrication iterations before obtaining a functional product. Substrate behavior is a significant contributor to such parasitics, and its modeling is a challenge, as nonuniform resistivity profiles are expected in semiconductor materials.
Novel Subthreshold Modelling of Advanced On-Chip Graphene Interconnect Using Numerical Method Analysis
Published in IETE Journal of Research, 2021
Nikita R. Patel, Yash Agrawal, Rutu Parekh
With the preferment of technology, the dimension of devices and interconnects scales down. At nano dimensions, interconnects start playing a dominant role in determining the overall performance of the system. At miniaturized technology nodes, overall system performance degrades due to parasitic effects of interconnect. Parasitic elements of the interconnects are capacitance, resistance and inductance. These causes delay, power dissipation and crosstalk in ICs. On-chip interconnects have thus become a major concerning factor and very important research topic nowadays [1].