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FinFETs
Published in Krzysztof Iniewski, Tomasz Brozek, Krzysztof Iniewski, Micro- and Nanoelectronics, 2017
Ideally, one would desire no doping in a FinFET channel. However, some light doping may be required to set alternative threshold voltages in certain devices or for better control of under-the-fin leakage current. Such doping is typically carried out with implantation. Source/drain doping, which requires high doses of dopant, faces a significant challenge in terms of increased series resistance. This is related to implant damage in the fins that, due to a fin’s geometry, is retained in higher amounts than in corresponding planar structures. Also, regrowth of the amorphized top part of the fin faces challenges in terms of very limited area of crystalline seed in the lower part of the fin and interactions of the regrowth process with sidewall surfaces of the fin [25–27]. High-temperature (300°C–400°C) implants [27], plasma-based doping [26], and so-called monolayer doping methods deliver dopants more conformally and with less damage to the fin. Alternatively, in situ doped epitaxial (“epi”) material is deposited in the source/drain area to deliver the dopant. This can be carried with or without removal of the fin in the source/drain area prior to epi.
Deterministic Single-Ion Implantation Method for Quantum Processing in Silicon and Diamond
Published in Simon Deleonibus, Integrated Nanodevice and Nanosystem Fabrication, 2017
Takahiro Shinada, Enrico Prati, Takashi Tanii
Monolayer doping, combined with spike annealing, promises fast doping of entire wafers in a single shot, and has proved effective for introduction of P and B on diethyl 1-propylphosphonate (DPP) and allylboronic acid pinacol ester (ABAPE), respectively.43 The monolayer doping method was successful to create controlled nanoscale doping at the near surface of semiconductor materials, by taking advantage of the self-limiting surface reaction properties of Si, followed by spike annealing. Diffusion of dopants and unwanted contaminants such as C and O atoms forming the precursor have been characterized and can be appropriately taken into account.44
Performance enhancement of core-shell JLFET by gate/dielectric engineering
Published in International Journal of Electronics, 2020
An RCS based P-DGJLFET 3-D structure and its cross-sectional view is shown in Figure 1. Unlike the conventional junctionless structure, the core and shell are doped with donor and acceptor impurities, respectively. The n-type core is inserted between the p-type shells to deplete the charge carriers completely in the bulk of the device. The n-type core will always be depleted due to the presence of oppositely doped shells whether the device is on or off condition. As the gate voltage increases, the holes in the shell regions start accumulating. These holes will then deplete the core even more. On further increasing the gate voltage, the holes start moving through the channel at the core/shell interface thus contributes in the current making the device as P-DGJLFET. During the simulation, the core thickness is varied from 1 to 4 nm and shell thickness is varied from 4.5 to 3 nm. Initially, core thickness is kept at 2 nm and shell thickness is at 4 nm each. The total thickness of core and shell is 10 nm and the length of the channel is kept at 5 nm in the entire work. The 3-D structure of RCS based DGJLFET has donor doped core whose concentration is varied from 1e+15 cm−3 to 1e+19 cm−3 and acceptor doped shell whose concentration is kept constant at 1.5e+19 cm−3. The dimensions and simulation parameters are listed in Table 1. In dual gate structure, the front gate and back gate are connected together. To validate the simulation models, the experimental results of conventional P-DGJLFET has been reproduced. The device simulations are performed using Visual Technology Computer Aided design (TCAD) software (Simulator, n.d.). In order to obtain a heavily doped core and shell with opposite doping in double gate structure, a uniform and steep doping can be done by molecular monolayer doping process which is already experimentally realised (Fan et al., 2007; Javey et al., 2009). The Random dopant Fluctuation (RDF) which is one of the major challenges of junctionless devices can be reduced by molecular monolayer doping which is applicable for both types of doping (n- and p-type) and can be fabricated by any one of the bottom-up or top-down approaches making the nanoscale semiconductor devices highly versatile for various applications (Fan et al., 2007; Lee et al., 2015). The proposed device structure with different dielectric and gate electrode materials can be fabricated using these techniques.