China
Africa
Explore chapters and articles related to this topic
Design Flows
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
Leon Stok, David Hathaway, Kurt Keutzer, David Chinnery
In newer libraries, the delays of gates with different logic complexities started to vary significantly. Table 1.1 shows the relative delays of different types of gates. The logical effort indicates how the delay of the gate increases with load and the intrinsic delay is the load-independent contribution of the gate delay. The FO4 delay is the delay of one gate of the specified type driving four identical gates of the same size. The fourth column of the table shows that the delay of a more complex NOR4, driving four copies of itself, can be as much as three times the delay of a simple inverter. The logical effort-based calculation to compute this already assumes that the gates have been ideally sized to best match the load they are driving. Simple addition of logic levels is therefore becoming insufficient, and one needs to know what gates the logic is actually mapped to, to predict the delay of a design with reasonable accuracy. It became necessary to include a static timing analysis engine (Chapter 6) in the synthesis system to calculate these delays. The combination of timing and synthesis was the first step on the way to the era of integration. This trend started gradually in the 1980s; but by the beginning of the 1990s, integrated static timing analysis tools were essential to predict delays accurately. Once a netlist was mapped to a particular technology and the gate loads could be approximated, a pretty accurate prediction of the delay could be made by the timing analyzer.
A systematic design of novel energy efficient 64-bit parallel-prefix adder
Published in International Journal of Electronics, 2021
Jagadeeshkumar N, Meganathan D
Table 5 shows the logical effort (g) and parasitic effort (p) of the logic circuits in high performance technologies. The logical effort is the ratio of gate capacitance of the logic circuit to the INV gate capacitance. Similarly, the parasitic effort is the ratio of drain capacitance of logic circuit to the gate capacitance of the same logic circuit. It has been observed from Table 6 that as the technology scales down, the logical effort and parasitic effort of complex logic circuits (NAND, NOR and XOR) are weakened down. Therefore, adding buffer stage provides an energy efficient solution (Zeydel et al., 2010).