China
Africa
Explore chapters and articles related to this topic
Magnetic disk drives
Published in John Watkinson, The Art of Digital Audio, 2013
These steps are the first line of defence against errors in disk drives, and serve to ensure that, by and large, the errors due to obvious surface defects are eliminated. There are other error mechanisms in action, such as noise and jitter, which can result in random errors, and it is necessary to protect disk data against these also. The error-correction mechanisms described in Chapter 7 will be employed. In general each data block is made into a codeword by the addition of redundancy at the end. The error-correcting code used in disks was, for a long time, Fire code, because it allowed correction with the minimum circuit complexity. It could, however, only correct one error burst per block, and it had a probability of miscorrection which was marginal for some applications. The advances in complex logic chips meant that the adoption of a Reed–Solomon code was a logical step, since these have the ability to correct multiple error bursts. As the larger burst errors in disk drives are taken care of by verifying the medium, interleaving in the error-correction sense is not generally needed. When interleaving is used in the context of disks, it usually means that the sectors along a track are interleaved so that reading them in numerical order requires two revolutions. This will slow down the data transfer rate where the drive is too fast for the associated circuitry.
From PICAP I to PICAP II
Published in K. S. Fu, Ichikawa Tadao, Special Computer Architectures for Pattern Processing, 1982
Björn Kruse, Per-Erik Danielsson, Björn Gudmundsson
Another way to reduce the effective access time is to split the memory into a number of separate modules which can be activated independently of each other. In a multiprocessor system this allows several processors to access memory simultaneously. It should be noted that memory access time is not improved by interleaving but only the potential gross data rate. Thus, if a processor can issue a new memory request only after processing of the previously fetched item, then interleaving is of no value. However, in picture processing the normal case is that a huge amount of data in memory is predetermined to be accessed in a certain order (mostly in a TV-scan pattern) and processed in a pipeline fashion, i.e., the processor overlaps successive references. Then the gross data rate of the interleaved system can be fully exploited even in a uniprocessor system. As can be seen in Figure 7, this approach is also used in PICAP II.
Low-Power Baseband Processors for Communications
Published in Christian Piguet, Low-Power Processors and Systems on Chips, 2018
Interleaving is an operation often carried out as part of the channel coding in a radio system. The purpose of interleaving is to distribute transmitted bits in time, frequency, or both. Consecutive bits on the input stream should not be transmitted consecutively in time (or on the same frequency in an OFDM system). Interleaving reduces the effect of burst errors caused by fast fading. The requirements for interleaving depend both on the modulation and error correction schemes used, and on the channel characteristics.
Energy efficient VLSI decoder chip with reduced PAPR in FECG monitoring
Published in International Journal of Electronics, 2020
D Preethi, R S Valarmathi, Harikumar R
In Figure 11, various PAPR reduction techniques such as clipping and filtering (CF), companding (CP), selective mapping (SLM), partial transmit sequence (PTS), interleaving, active constellation shaping (ACS), constrained constellation shaping (CCS), linear block coding (LBC) and tone reservation (TR) are validated for recovery of data. Among the various techniques, CF leads to high BER owing to in-band distortions; CP provides reduced PAPR with increase in average power. SLM has high computation complexity of O (n log (n)) since different data blocks of same information are transmitted multiple times. Hence, in all the three techniques data recovery time is slow at a rate of 40–60%. Though the other strategies of PTS, ACS, CCS and LBC offer nearly faster data recovery time of 20–25%, still has certain setbacks on searching best-fit phase vector for transmitting side information along with data with reduced gain efficiency. Whereas, tone reservation overcomes the aforementioned drawback with low computational complexity of O (log (n)) and data recovery time is fastest at a rate of 8.5%.
Dynamics and circuit of a chaotic system with a curve of equilibrium points
Published in International Journal of Electronics, 2018
Viet–Thanh Pham, Christos Volos, Tomasz Kapitaniak, Sajad Jafari, Xiong Wang
A considerable amount of literature has been published on chaotic systems (Genesio, Tesi, & Angeli, 1995; Hramov, Koronovskiy, Kurkin, & Rempen, 2011; Skorupka, Krowne, & Pecora, 1994; Stavrinides, Papathanasiou, & Anagnostopoulos, 2015; Wang, Meng, Sun, & Guo, 2017). Complex behaviours of chaotic systems are useful for various practical applications such as communications (Liao & Chen, 1999), block cipher adapted to image encryption (Faragallah, 2012), interleaving scheme for multiplexing systems (Hassan et al., 2013), and complex Bernoulli spreading codes for DS-CDMA systems (Sabahi & Dehghanfard, 2014). Therefore, theoretical study and circuit implementation of chaotic systems are important topics in electronics engineering (Elwakil & Kennedy, 2000; Giannakopoulos & Deliyannis, 2005; Gopakumar, Premlet, & Gopchandran, 2011; Muñoz-Pacheco, Tlelo-Cuautle, Toxqui-Toxqui, Sánchez-López, & Trejo-Guerra, 2014; Saito, Jinno, & Torikai, 1995).
Analog-to-information conversion by encoded multi-cosets
Published in International Journal of Electronics Letters, 2020
Now, to reduce computational complexity, the transfer functions Hp(z), for p = 0, 1, .., P–1, are decomposed in Q polyphase branches, length l each. Since these branches have equal de-interleaving front-ends, a Multiple Input Multiple Output (MIMO) polyphase array is formed for all of them sharing the de-interleaving block. From this scenario, we have that the time-multiplexing back-end of the TI-ADC and the de-interleaving front-end preceding the MIMO polyphase array establish the following relation: