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Commercial VLSI RISC
Published in S.B. Furber, VLSI Risc Architecture and Organization, 2017
operand value itself (in the case of an immediate operand), or the address of the operand (absolute addressing and stack pointer relative) or the address which contains the operand address (indirect addressing). The Operand Register stage contains the actual operand values. The Result Register stage contains the result of combining the operands in the specified way. Each stage may be controlled by a different instruction at any point in time. A particular instruction begins execution by moving from the decoded instruction cache into the Instruction Register. The operand address registers are added to the stack pointer for stack pointer relative direct or indirect addressing, and two 28-bit adders are dedicated to this function. Here any references to off-chip memory must be detected and the data items read in; indirect addressing requires two such memory accesses. Memory accesses which happen to use addresses currently contained in the on-chip stack cache must be detected and the values located. The values are moved into the Operand Registers, and when they have both been loaded the instruction moves on to the Operand Register stage and frees up the Instruction Register stage for the next instruction. Note that the stack cache is dual parted, so that if both operands refer directly to memory which is in the stack cache, then both operands can be located and fetched in one cycle. The instruction may only occupy the Instruction Register stage for one cycle even though it apparently requires two memory accesses to complete. The instruction moves to the Result Register stage by processing the operands in the ALU. The values in the Operand and Result Registers are all 32-bit words, so byte and halfword values must be aligned (by shifting) and sign extended on their way into the 32-bit ALU, and a byte or halfword
The outstation
Published in G.J. Levermore, Building Energy Management Systems, 2013
The next step of the control program is read by the CPU from the RAM. A program counter in the CPU locates the relevant program step and loads it into the CPU’s instruction register. This instructs the CPU to take from the EPROM a small control element program; the CPU then runs this program to compare the temperature reading with a temperature setpoint in the RAM, chosen by the user. This is all done by fetch and execute operations, each taking only approximately 250 ns to perform.
Computer Engineering
Published in Arun G. Phadke, Handbook of Electrical Engineering Calculations, 2018
Peter Athanas, Yosef Tirat-Gefen
In the remainder of this section, an illustrative example will be used to expound upon the relationship between the control and data implementation of the organization of a very simple accumulator-based processor (shown in Fig. 6.5). This processor is organized using a single bus (labeled A-bus in the figure), which is shared with all of the resources within the processor. All of the rectangular objects in the figure denote registers that, when selected by the control unit, capture data from the A-bus on the rising edge of a clock signal (which is not explicit in Fig. 6.5, yet is implied). When directed by the controller, the registers can transfer data onto the A-bus by using tri-state drivers or multiplexors. The ISA for this processor specifies the existence of an accumulator (which registers the output of the ALU) and two general-purpose registers, RO and Rl. The instruction register (IR) contains the current instruction being executed, and the program counter contains an address that points to the next instruction (in memory) to be executed. Two memory support registers are also explicit in this organization: MDR and MAR. MAR (the memory address register) contains the address of the current location being referenced in memory. The MDR (memory data register) serves two functions in this organization. When data are transferred from the A-bus to the MDR, the processor initiates a memory write cycle, where the new data in MDR are moved to the location specified by MAR. When a transfer is requested from MDR to the A-bus, a memory read cycle is initiated (data from the location referenced by MAR are transferred to MDR and A-bus). The register labeled temp is not part of the ISA specification, but is provided in the organization to facilitate the execution of ISA-specified instructions.
Synthesis of programmable biological central processing system
Published in Journal of the Chinese Institute of Engineers, 2021
Wei-Xian Li, Jiangfeng Cheng, Chun-Liang Lin, Chia-Feng Juang
We designed the Bio-CPU in a manner analogous to that of the Von Neumann architecture (Freeman 2017). Figure 9 depicts the idea, which involves three core parts: MU (to serve as random access memory), CPU, and signal transmission bus. In an electronic product, the input and output might be a keyboard and a screen, respectively. In a biological system, the input and output rely on certain promoter and protein concentrations. In the proposed system, the MU is used for data and instruction storage. The CPU contains an ALU and several processor registers (in particular, a CU contains an instruction register and a program counter). The ALU serves as the core center for data manipulation and calculation. All of the previously developed modules (including genetic logic gates, genetic clock generators, and all other combinational and sequential genetic circuits) were used to assemble these core subsystems.