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Challenges to FinFET Process and Device Technology
Published in Samar K. Saha, FinFET Devices for VLSI Circuits and Systems, 2020
The high-k dielectric along with metal gate process is used for advanced CMOS technology due to the high dielectric constant and a relatively large bandgap of the high-k dielectric [43]. Typically, HfO2 high-k dielectric with high permittivity (a dielectric constant of about 25) and a relatively large bandgap (5.7 eV) is used as the gate dielectric for both the nFinFET and pFinFET devices (Table 9.1) [9]. In addition, the HfO2 has high heat of formation, good thermal and chemical stability on silicon, and large barrier height at interfaces with silicon. And, at an operation voltage of 1–1.5 V, the leakage current through HfO2 dielectric films is several orders of magnitude lower than that through SiO2 films with the same equivalent oxide thickness (EOT) [35,43]. However, one of the main challenges of HfO2 integration for sub-22 nm FinFETs is the thermal instability of HfO2/silicon interface. There is an inevitable SiOx interlayer between HfO2 and silicon substrate [43–45], even though the HfO2/silicon is theoretically found to be thermodynamically stable [46]. Table 9.1 shows the relevant high-k HfO2 dielectric and metal gate technology parameters for 22 nm and 14 nm technology nodes [9]. The table also shows the use of TiAlN and TiN metal gates for nFinFETs and pFinFETs, respectively.
Fabrication Issues
Published in He Iwong, Nano-Cmos Gate Dielectric Engineering, 2017
Looking at the high-k gate dielectric itself, we require deposition techniques for depositing the thin high-k materials at excellent uniformity, and the etching of the high-k layer is another big challenge. There are several deposition techniques being developed for the deposition of high-k dielectric layers, such as physical vapor deposition (PVD), metallo-organo chemical vapor deposition (MOCVD), and atomic layer deposition (ALD). These methods have their own advantages and disadvantages. The PVD method has a constraint on the aspect ratio of structures to have a perfect coverage. CVD has the advantage of good step coverage, but it often suffers from the contamination of various impurities from the precursors. Atomic layer deposition (ALD) has advantages of low process temperatures and precise thickness control of thin film down to the atomic scale. However, it still suffers from the contamination of the metal-organic precursors.
2 Thin Film for Microelectromechanical Systems Application
Published in Iniewski Krzysztof, Integrated Microsystems, 2017
The surface damage inherent in a sputtering PVD process and device morphology inherent to the scaling process generally rule out PVD deposition approaches. Within all the manufacturing options, chemical vapor deposition-based methods, ALD and MOCVD, draw the highest industrial interest for deposition of high-k dielectrics. ALD approaches appear to be promising, because of its precision in layer growth and high layer uniformity in large deposition areas such as 300 mm wafer technology. However, the generation of polycrystalline dielectrics in the manufacturing environment may cause high leakage currents and a possible diffusion path for dopants along its grain boundaries. Another major disadvantage of ALD is the long processing time, which makes it an expensive tool to operate. Besides, the demand for complex precursors decreases its flexibility for using in material research. The other technique is MOCVD, because of its good film conformality and control on deposition rates. However, choice of the precursor, deposition temperature, and incorporation of carbon impurities are major concerns in this technique.
Sentaurus TCAD simulation of SET and Radiation-Hardened technology for FDSOI TFET devices
Published in Radiation Effects and Defects in Solids, 2023
Shougang Du, Hongxia Liu, Shulong Wang
The subthreshold swing (SS) is one of the main parameters to characterize the switching characteristics of devices. The subthreshold swing can be reduced by reducing 1+ Cd/COX. One method is to adjust the process material of the device. The typical way is to reduce the depletion capacitance Cd by minimizing the substrate doping concentration and interfacial charge density. Another way is to increase the gate oxygen capacitance COX. Since the gate oxygen parallel plate capacitance is proportional to ϵ/TOX, high K dielectric materials are mostly used to replace SiO2 as the gate oxygen material (1–3). However, with the reduction of the characteristic size of the device, in order to ensure that the gate leakage is in a considerable range, the thickness of gate oxygen, Tox, cannot be unconditionally reduced. Therefore, the improvement of COX by using a high K medium is limited.
A Simulation Approach for Depletion and Enhancement Mode in β-Ga2O3 MOSFET
Published in IETE Technical Review, 2022
Pharyanshu Kachhawa, Nidhi Chaturvedi
Furthermore, the effect of different gate dielectrics for the gallium oxide MOSFET has been simulated [12]. The effect of three different dielectrics on gallium oxide MOSFET performance are explored considering same dielectric thickness = 10 and 150-nm active gallium oxide channel thickness. This material includes SiO2 (k = 3.9) and Al2O3 (k = 10) and high-k dielectric HfO2 (k = 25). Gate dielectrics are incorporated with their respective interface densities 6e11, 2.3e11, and 1.3e11/cm2.eV to check their realistic results on the device performance [20,21]. The different gate dielectric has been performed on the 15-nm active channel gallium oxide MOSFET. The high-k dielectrics give better performance in terms of decreased Ioff current, better Ion, better subthreshold slope, and improved threshold voltage due to its high interface density and material properties. A comparison of Ioff current and subthreshold slope is also shown in Figure 7 with respective gate dielectric material. All the extracted parameters (15 nm active channel) are shown in Table 3 for a comparison.
TCAD Investigation for Dual-Gate MISHEMT with Improved Linearity and Current Collapse for LNAs
Published in IETE Technical Review, 2022
Preeti Singh, Vandana Kumari, Manoj Saxena, Mridula Gupta
The single-gate AlGaN/GaN HEMT structure (gate length, LG = 140 nm) which is used in this work is based on an experimental device reported by Ide et al. [36] and the schematic of single-gate MISHEMT is illustrated in Figure 1(a). The device structure consists of i-AlGaN cap layer (5 nm), n-doped AlGaN barrier layer (20 nm), i-AlGaN spacer layer (2 nm) (to minimize alloy scattering), and mole fraction for AlxGa1-xN layers is x = 25%. The undoped GaN buffer layer is of thickness, tbuffer = 3 µm and followed by sapphire substrate. For AlGaN/GaN MISHEMTs (illustrated in Figure 1(a) and (b)), high-K dielectric HfO2 has been used as gate dielectric (∼6 nm) underneath gate contacts and as passivation layer. The other dimensions such as gate-to-source distance (LGS)/gate-to-drain distance (LGD) for single gate are 500 nm/500 nm. The cross-sectional diagram of DG-MISHEMT is depicted in Figure 1(b). Dimensions for dual-gate devices LG1S/LG1G2/LG2D are 260 nm/100 nm/500 nm, respectively, where G1 and G2 corresponds to gate 1 (control gate) and gate 2 (screen gate).