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Fundamentals of Microfabrication Technologies
Published in Ghenadii Korotcenkov, Handbook of Humidity Measurement, 2020
The most common hard-mask material is silicon dioxide. The popularity of silicon dioxide is based on its well-explored material properties and designed growth, deposition, and etching techniques. The etch rate of SiO2 during DRIE of silicon is very low, which makes the creation of deep structures possible. According to French et al. (1997), the ratio of etch rates Si/SiO2 could change from 370 for etching in SF6/O2 up to 20 for etching in Cl2/BCl3/H2. The thermal growth of SiO2 requires temperatures around 1000°C, which limits its use. Plasma-enhanced chemical vapor deposition (PECVD) can be done at considerably lower temperatures (ca. 300°C). In plasma etching, the etch rate of PECVD oxide is comparable with thermal oxide (Buhler et al. 1997).
k Integration
Published in Robert Doering, Yoshio Nishi, Handbook of Semiconductor Manufacturing Technology, 2017
Girish A. Dixit, Robert H. Havemann
Figure 2.8d depicts one of the trench first dual damascene sequences with two hard mask layers [52,53]. The sacrificial hard mask stack is comprised of a dielectric/metal nitride bilayer. Materials such as titanium nitride may be used as a metal hard mask. The optical transparency of this material is a key requirement to ensure alignment between the successive pattern steps and the transparency requirements limit the useable thicknesses of these films. The process steps typically involve pattern and etch of the trench features into the metal hard mask followed by via pattern. Following via etch; a sacrificial fill of via may be utilized prior to completing the trench etch with the metal nitride mask. Typical post-etch resist removal processes include an oxidizing plasma which in turn may also cause oxidation and loss of carbon from the sidewalls of the trench features. The oxidation damage to low-k materials is undesirable as it leads to an increase in the dielectric permittivity. Due to the absence of resist following the trench etch, an oxidizing plasma clean is unnecessary and the post-etch clean may be accomplished through the use of solvents, thus eliminating the risk of oxidizing the low-k material. This approach involves a metal etch step to define the trench into the metal nitride and this may require additional process equipment compared to the approaches without metal hard masks. Table 2.4 summarizes the challenges in the various dual damascene schemes.
Biosensing Based on Surface- Enhanced Raman Spectroscopy
Published in Li Jun, Wu Nianqiang, Biosensors Based on Nanomaterials and Nanodevices, 2017
Logan Liu Gang, Zheng Wenwei, Zhang Pingping, Chen Fanqing (Frank)
A potential low-cost, large-scale method for SERS substrate fabrication is nanoimprint lithography (NIL). The process is twofold: a hard mask, typically made of metal, dielectrics, or a semiconductor material, is pressed into a thin layer of polymer heated above its glass transition temperature [86]. When pressed together, the viscous polymer conforms to the mold topography, creating thickness variations in the substrate upon the removal of the mold [87]. A reactive ion etch (RIE) of the substrate completes the pattern transfer. NIL processes have been used to create gold rectangular, cylindrical, and diamond-shaped nanoblocks based on grating mold orientation [88], flat, grated, and pillared silver nanostructures for SERS [89], and gold nanodisks [90]. A potential disadvantage of the NIL process is the embedded cost of fabricating the original mold, which requires access to high-resolution lithographic tools, such as EBL. The mold-making process involves placing resist on the mold substrate, nanopattern exposure, hard mask (metal) deposition on the template, followed by liftoff and RIE for the selective etching of the mold [91]. Once the NIL mold is fabricated, multiple transfers provide a high level of repeatability for nanoscale features.
Characterisation of a Schottky ISFET as Hg-MOSFET and as cytochrome P450-ENFET
Published in International Journal of Electronics, 2018
Chinmayee Hazarika, Dhrubajyoti Sarma, Sujan Neroula, Kritanjali Das, Tapas Medhi, Santanu Sharma
A 3-in double-sided polished p-type (100) silicon wafer of resistivity of about 0–5 Ω cm has been used as the substrate for the ISFET device. The wafer is boron doped and has a thickness of about 370 μm. The normal standardised procedure of cleaning has been done on the wafer which involves degreasing to remove wax or any oil contamination. The RCA cleaning process is carried out further to remove organic and metallic contaminants (May & Sze, 2004). The cleaning process is followed by deposition of 480 nm thick silicon dioxide (SiO2) by thermal oxidation technique at a temperature of 1050°C with a gas flow of 2 slpm (standard liquid per minute) of oxygen as depicted in Figure 1(a). The duration of deposition was 30 min/1 h/30 min (dry oxygen/wet H2O/dry oxygen). First level of lithography outlines the area (the active area along with the protective region so that metal does not come in direct contact with that of the active area) to be etched using the first mask (inset a). Dimension of the said area is 22 × 7 mm2. The unmasked region has been removed by using buffer oxide etchant for the metal to be directly deposited in the unmasked region to form the Schottky contacts in the later stage. The second lithography has been done to etch out an active area of dimension 5 × 5 mm2 by using second mask (inset b). A hard mask has been used as the third mask for the metal deposition (the first mask is used again as hard mask). This hard mask avoids the necessity for another level of lithography. This hard mask is a transparent sheet with the imprints of the first mask used with openings at the region where metal is to be deposited. This mask is attached to the wafer with Kapton tape (Polymide film which can sustain high temperature). Further, silver was deposited on the exposed region thus forming the Schottky contacts. Deposition of silver has been done by thermal evaporation with a 60–70 A current for a duration of 30 s, resulting into metal deposition of 120 nm thickness. The silicon substrate was then mounted on PCB board with adhesive. Male connectors were soldered in the PCB board for the connections of source and drain. The connectors were bonded to the metal layers using silver paste. A glass chamber constructed employing cover slip has been used for the deposition of electrolyte over the active layer. Silicone which is found to have negligible effect in pH of different values was used for passivation and sealing purpose (Mowrer, 2003). Figure 1 depicts the schematics of the process flow involved in the fabrication process. The actual ISFET device is depicted in inset 1e.