China
Africa
Explore chapters and articles related to this topic
Bio-Inspired Solutions and Network on Chip (NoC) Fault Tolerant Algorithms
Published in Phan Cong Vinh, Nature-Inspired Networking: Theory and Applications, 2018
Muhammad Athar Javed Sethi, Fawnizu Azmadi Hussin, Nor Hisham Hamid
System on Chip (SoC) has seen a continuous increase of computational nodes on it. This has increased the communication requirement between them. Complexity of the communication has also increased due to these nodes. This leads scientists and researchers to think over a new communication paradigm. Time to market access is another major factor that forced the scientists to rethink the design of SoC architecture. Because of these requirements, scientists presented the idea of Multiprocessor System on Chip (MPSoC). This improved the performance and processing power of embedded systems. Philip Nexperia, TI OMAP, and ST Nomadik are a few MPSoC platforms available in the market today. As the numbers of devices increased, the interconnections of internal components of MPSoC became a major issue. The bus-based systems between these internal components were also not able to handle the Globally Asynchronous Locally Synchronous (GALS) concept. In the GALS approach every component works in a different clock domain. This further triggered the research for on-chip communication. Scientists started thinking over the reliable and efficient communication between MPSoC components. Later, they came up with the idea of Network on Chip (NoC) architectures to address the complex communication requirements of MPSoC. NoC have brought the packet switching concept into the on-chip communication. Today, a few of the commercially available NoC’s are Arteris, Silistrix, and INoC [1,35].
Asynchronous Wrapper-Based Low-Power GALS Structural QDMA
Published in IETE Journal of Research, 2022
B.K. Vinay, S. Pushpa Mala, S. Deekshitha
GALS architectures comprise asynchronous wrappers constituting LS modules and port controllers to handle communication between various LS modules. The proposed design flow is depicted in Figure 3. The IP functionality is defined using Hardware Description Language on Vivado Tool Suite at the RTL development stage. The IP integrator in Vivado interconnects various IP cores by instantiating them to build the final Queue Direct Memory Access (QDMA) module. Design verification is done using the Vivado Simulator to verify specific functionalities of the QDMA module. The synthesized netlist generated is used to analyze the hierarchy of design and ensure design optimization by eliminating redundant logic modules. The syntax is verified, and the obtained netlist is saved as a Native Generic Circuit (NGC) file.