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Health Monitoring Based on Internet of Things (IoT)
Published in Rajarshi Gupta, Dwaipayan Biswas, Health Monitoring Systems, 2019
Domenico Balsamo, Saptarshi Das
In order to achieve power neutrality, different control schemes are used to adjust the power consumption dynamically depending on the type of processing unit. In smaller-sized single-core MCUs, dynamic frequency scaling (DFS) can be used in which the clock frequency of the processing element is adjusted to the specific power constraints, whilst with multicore systems more sophisticated techniques exist, such as dynamic voltage and frequency scaling (DVFS), where the supply voltage of the processing unit is also adjusted, and core hot-plugging technique to dynamically switch cores on or off. Different runtime approaches to manage and adapt these controls have been proposed for power-neutral management on both single and multicore systems [17,18].
Processor Physics and Moore’s Law
Published in Vivek Kale, Parallel Computing Architectures and APIs, 2019
Whereas the response time refers to how long the computer takes to do an activity, throughput refers to how much the computer does in unit time. The speed of a program execution can be measured in terms of Response time: The response time is measured by the time elapsed from the initiation of some activity until its completion. A frequently used response time metric is program ET, which specifies the time the computer takes to execute the program once.The ET of a program can be expressed as the product of three quantities: The number of instructions executed or the instruction count (IC).The average number of clock cycles required to execute an instruction or cycles per instruction (CPI).The duration of a clock cycle or cycle time (CT).Thus,ET=IC×CPI×CTAlthough the resulting ET can give a fair estimate of the ET, it can be rendered invalid because of inaccuracies in any one of the constituent factors: The IC of a program may vary depending on the data values supplied as input to the program.The CPI obtained may vary depending on what other programs are simultaneously active in the system.The computer systems may dynamically adjust the clock CT (dynamic frequency scaling) in order to reduce the power consumption.Throughput: Throughput specifies the number of programs, jobs, or transactions the computer system completes per unit time.
HANU: Heuristic Asynchronous NoC for universal power electronics application
Published in EPE Journal, 2020
Sakthivel Erulappan, Arunraja Muruganantham, Veluchamy Malathi
NoC is a booming area for designing Current application like multimedia, telecommunication, and real-time task [1]. The overall result of Power Electronics application will always be an NoC layout. Low power is provided to NoC [2], using PE circuits (DC-DC Converter). Currently, many academics are constructing their contribution to improve the parameters like complication, flexibility, power consumption and performance improvement on the single-core dies [3]. The problem of data synchronization for multi-clock-based SoCs leads to a performance disturbance. To achieve low power consumption and high operating speed, designers prefer the Dynamic Frequency Scaling algorithm (DFS) [4]. In [5], the Dynamic Voltage Scaling algorithm (DVS) resulted in a scalable architecture due to external circuit combinations of system configurations. To avoid this complication, dynamic frequency scaling is introduced in [6]. Typically, the DFS-based NoC area governs the target source devices and thus greatly manipulates the power consumption and enhances the clock distribution [7]. Table 1 shows performance comparison with the conventional methods.