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Semiconductor memory, input and output, and peripheral circuits
Published in D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader, Mechatronics, 2018
D.A. Bradley, N.C. Burd, D. Dawson, A.J. Loader
Some I/O related operations transfer large amounts of data to and from memory. However, occupying the CPU to move the contents of large blocks of data between memory and I/O devices is wasteful of the time that it could otherwise spend executing other more useful instructions. To move blocks of data, the CPU will have to repeatedly fetch and execute load and store instructions during which it may spend more time fetching instructions than it will moving the data. The CPU is therefore a bottleneck in that it restricts the fast transfer of data between memory and I/O, because for each transfer the data must pass through the CPU under the control of the program that the CPU is executing. A solution to this problem is to provide a data path directly between memory and I/O which is under the control of a dedicated device called a direct memory access (DMA) controller, as shown in Fig. 12.13. As its name suggests, a DMA controller provides I/O devices with direct read and write access to memory without the data passing through the CPU. However, because the DMA controller and the CPU make use of the same system bus, they must both implement a means by which they can share the bus without disturbing their operation.
D
Published in Phillip A. Laplante, Dictionary of Computer Science, Engineering, and Technology, 2017
DMA is used in a computer system when transferring blocks of information between I/O devices (e.g., disk memory) to/from the main memory with minimal intervention from the CPU. A DMA controller is used and can, after initiation by the CPU, take control of the address, control, and data busses. The CPU initiates the DMA controller with parameters such as the start address of the block in main memory, number of bytes to be transferred, and the type of transfer requested (Read or Write). The transfer is then completely handled by the DMA controller, and the CPU is typically notified by an interrupt when the transfer service is completed. While the DMA transfer is in progress, the CPU can continue executing the program doing other things. However, as this may cause access conflicts of the busses between the CPU and the DMA controller, a memory bus controller handles prioritized bus requests from these units. The highest priority is given to the DMA transfer, since this normally involves synchronous data transfer which cannot wait (e.g., a disk or tape drive). Since the CPU normally originates the majority of memory access cycles, the DMA control is considered as “stealing” bus cycles from the CPU. For this reason, this technique is normally referred to as cycle stealing. Compare with memory-mapped I/O, programmed I/O.
Parallel Input and Output
Published in Fernando E. Valdes-Perez, Ramon Pallas-Areny, Microcontrollers, 2017
Fernando E. Valdes-Perez, Ramon Pallas-Areny
In both I/O techniques, the data transmission speed between peripheral and microcontroller is ultimately limited by the speed in executing instructions, because this execution is based on reading or writing data using the appropriate instructions. Furthermore, the data transferred between memory and the I/O ports normally have to move through the CPU, thus further limiting the speed of the process. Microprocessor systems utilize a third I/O technique to bypass these limitations by using direct memory access (DMA). DMA is a hardware-implemented I/O technique based on the direct data transfer between peripheral and memory without having to execute a program, thus allowing for very high data-transfer rates. This technique is, however, used in very few microcontrollers. None of the PIC microcontrollers use DMA for I/O.
Multi-channel non-destructive testing of steel strip stress based on magneto-elastic effect
Published in Nondestructive Testing and Evaluation, 2023
Mingyang Yu, Bin Wang, Bo Li, Boyang Zhang, Qingdong Zhang
The workflow of the well-debugged circuit system is as follows: FPGA obtains a 50 Hz frequency signal input MOS FET through active crystal frequency division. The constant voltage source provides 8.5 V DC input FET, thereby generating a square wave signal with a frequency of 50 Hz and an amplitude of 8.5 V in the excitation circuit. Adjusting the inductance or capacitance in the series resonant circuit can change the amplification degree of the square wave signal. The larger the amplitude of the excitation voltage, the stronger the induction signal, but the mutual interference of the sensors will be more serious. Therefore, on the premise of meeting the detection accuracy, the excitation voltage amplitude should not be too large. After the test, the sinusoidal current with an amplitude of 90 V and a frequency of 50 Hz is selected to input the excitation probe to generate a changing magnetic field on the strip. The influence of the low-frequency eddy current on the magnetic permeability can be ignored [32]. An induced current will be generated in the induction coil of the induction probe. The induced current is filtered and amplified for preprocessing, and the MC33274 operational amplifier is used in the filter amplification circuit. The preprocessed analog signal is sent to the A/D converter, converted into a digital signal, and the data is transferred to the FPGA buffer. When the data buffered in the FPGA buffer reaches a certain amount, the FPGA transfers the data to the ARM processor through DMA. The ARM processor outputs the processed signal to the back-end host through the serial port, displays and stores the curve graph through the interactive interface, and stores the data in the SD card through the USB interface for data backup. The final voltage signal output interface is shown in Figure 4. The voltage signal curve in the figure represents the process in which the external mechanical load received by the tested strip gradually increases, then remains stable, and then gradually unloads.