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Performance Study on Switch and Network
Published in Naoaki Yamanaka, High-Performance Backbone Network Technology, 2020
The asynchronous transfer mode (ATM) concept is believed to well support high-speed multimedia infrastructure. ATM networks are able to handle various services, such as high-speed data communications, realtime video conferences, and High-Definition Television broadcasting. Input and output buffering switches are one type of crossbar switch. This chapter proposes a new input and output buffering switch architecture, named the Tandem-Crosspoint (TDXP) switch, under the consideration on device technologies. The TDXP switch has, logically, multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Input and output buffering switches are one type of crossbar switch. An advantage of the crossbar switch is scalability. Variants of crossbar-type switches include the input buffering switch and the output buffering switch. To implement ATM switches that have much larger throughput than conventional switches cost-effectively, one need a new switch architecture that does not increase the internal line speed nor does it have to rebuild cell sequences at the output buffers.
Parallel and high-performance systems
Published in Joseph D. Dumas, Computer Architecture, 2016
The highest-performance dynamic interconnection network is a single-stage network known as a crossbar switch, specifically a full crossbar (so termed to distinguish it from a staged network made up of smaller crossbar switching elements). An m × n crossbar switch is a hardware switching network with m inputs and n outputs (usually, but not always, m = n) in which a direct connection path can be made from any input to any output. The hardware is so duplicated that no connection interferes with other possible connections; in other words, making a connection from input i to output j does not prevent any input other than i from being connected to any output other than j. At any time, several independent, concurrent connections may be established (as many as the smaller of m or n), subject only to the restriction that a given input can only be connected to one output and vice versa.
Switching Architectures for ATM Networks
Published in Abhijit S. Pandya, Ercan Sen, for Broadband Telecommunications Networks, 2018
The switching networks can be classified into two categories, blocking and non-blocking, in terms of their internal blocking characteristics. An N×N non-blocking switching network allows N input-output pairs to be connected simultaneously, given that these pairs are disjoint. The best known non-blocking switch is the crossbar switch. A typical 4×4 crossbar switch is shown in Figure 7-5. It consists of an array of 4×4 cross-point switches representing each input-output pair.
An inventive high-performance computing electronic information system for professional postgraduate training
Published in International Journal of Computers and Applications, 2020
Wenzhun Huang, Peng Wang, Lintao Lv, Liping Wang, Harry Haoxiang Wang
On-chip network topology research focuses on reducing transmission delays and improving throughput. High-level topologies such as Flatten Buttery and Multi-drop Express Channels have emerged, making full use of on-chip rich connection resources. In terms of router micro-architecture design, people have proposed Performs virtual channel allocation and crossbar switch allocation in parallel, using guessing to reduce router pipeline progression. Under pressure from low power consumption and energy efficiency, dedicated hardware accelerator has become the most attractive high-performance processing component but choosing special accelerator usually means the partial loss of generic programming features, and causes an additional effort on development, debugging, and maintenance. At the same time, the special accelerator is also subject to application in the field of the rapid evolution and potential field change, often leading to repeated design and validation overhead.
Determining the reliability importance of switching elements in the shuffle-exchange networks
Published in International Journal of Parallel, Emergent and Distributed Systems, 2019
Fathollah Bistouni, Mohsen Jahanshahi
Figure 7 shows terminal reliability importance as a function of time for various switching elements in 8 × 8 SEN+. In this analysis, according to research conducted on C.mmp system [66] (C.mmp is a canonical multiprocessor system with a 16 × 16 crossbar switch) and also based on [22], it is assumed that a reasonable estimate for the failure rate of 2 × 2 crossbar switch is equal to 0.0000017 per hour. As can be seen in Figure 7, switches in the first and last stages are more appropriate options to improve terminal reliability of SEN+ compared to the middle stage switches, especially for less working hours.
Performance centric design of subnetwork-based diagonal mesh NoC
Published in International Journal of Electronics, 2019
Tuhin Subhra Das, Prasun Ghosal
In implementing the proposed method, instead of considering any complex router architecture like parallel CDMA CODEC (Wang, Guo, Chen, Li, & Lu, 2018), we select generic crossbar switch architecture. This is due to the simplicity in implementing a high radix router using a crossbar switch that offers concurrent data transmission on routers different ports. On the contrary, transmitting data parallel in CDMA switch increases router cost too high because of the additional circuitry used for duplicating the encoding and decoding unit for each transmitted data bit (Wang, Ahonen, & Nurmi, 2007).