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Digital fundamentals
Published in David Wyatt, Mike Tooley, Aircraft Electrical and Electronic Systems, 2018
A bistable device is a logic arrangement that is capable of ‘remembering’ a transient logic state such as a key press or a momentary overload condition. The output of a bistable circuit has two stable states (logic 0 or logic 1). Once set in one or other of these states, the output of a bistable will remain at a particular logic level for an indefinite period until reset. A bistable thus forms a simple form of memory as it remains in its latched state (either set or reset) until a signal is applied to it in order to change its state (or until the supply is disconnected).
Electronic Devices and Communication Applications
Published in Mike Tooley, BTEC First Engineering, 2010
By contrast, the output of a bistable has two stables states (logic 0 or logic 1) and, once set the output of the device will remain at a particular logic level for an indefinite period until reset. A bistable thus constitutes a simple form of memory circuit because it will remain in its latched state (known as set or reset) until commanded to change its state (or until the supply is disconnected). In other words, it remembers the state that it is placed in. Various forms of bistable are available including R-S, D-type and J-K types.
Logic Circuits
Published in Mike Tooley, Aircraft Digital Electronic and Computer Systems, 2023
The output of a bistable circuit has two stable states (logic 0 or logic 1). Once set in one or other of these states, the output of a bistable will remain at a particular logic level for an indefinite period until reset. A bistable thus forms a simple form of memory as it remains in its latched state (either set or reset) until a signal is applied to it in order to change its state (or until the supply is disconnected).
Comparative Analysis of Delay-Based and Memory-Based Physical Unclonable Functions
Published in IETE Technical Review, 2022
Priti S. Lokhande, Sangeeta Nakhate
SR Latch PUF is proposed by Hata and Ichikawa [21] which utilizes the concept of bistable elements and Butterfly PUF. The structure is made up of two NAND gates-based SR latches as shown in figure 7. The latches are cross-coupled to create the bistable structure. The latch offers four possible states for S and R inputs. When S = R = 0, it indicates that the output does not change, S = 0 and R = 1 indicate that the output is reset to 0, S = 1 and R = 0 indicate that the output is set to 1 and S = R = 1 indicates that the output is unstable. EN is attached to one of the SR latches’ input pins. When the EN pin receives a high pulse, the circuit becomes unstable. Two NAND gates, however, have slightly varying delays due to differences in the manufacturing process, which makes one of the feedbacks stronger. Thus, after an indeterminate amount of time, the outputs transition to a stable state. The input and output of the circuit are enhanced using flip-flops to increase the number of mismatches. There is no need to be concerned with the symmetry of the circuit before the flip-flops because all of them are triggered by the same clock. This is because the clock reaches the flip-flops before the signal reaches the SR latches. NAND gates are substituted with LUTs in the SR latch PUF since LUTs are employed in FPGA to implement logical functions. By including multiplexers to choose which SR latch gives the response bit, Ardakani and Shokouhi modified the SR latch design to support CRPs [22]. According to experimental findings, the Intra-HD is less than 20%, whereas the Inter-HD is approximately 49.2%.