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Macgic, a Low-Power Reconfigurable DSP
Published in Christian Piguet, Low-Power Processors and Systems on Chips, 2018
Flavio Rampogna, Pierre-David Pfister, Claude Arm, Patrick Volet, Jean-Marc Masgonty, Christian Piguet
The first programmable DSPs were relatively simple microprocessors, specialized in the handling of very specific data formats: either fixed-point or floating-point, depending on their architecture [9,10,13,17,19]. These processors were very efficient in transferring data between the memory and their data processing unit, as well as in the processing of the data itself. The data processing unit was typically optimized for the handling of multiply-and-accumulate (MAC) operations between two data words read from two different memories. Memory accesses were indirect, and most DSPs supported modulo indirect addressing modes especially useful in convolutions or for implementing circular buffers. Sometimes, a special reverse-carry addressing mode was also available, and was useful for the reordering of the data in fast-Fourier-transform (FFT) computations. The address computation hardware was typically located into address generation units (AGUs). An AGU usually contains a set of specialized index, offset and modulo registers.
Digital Signal Processors
Published in Nihal Kularatna, Electronic Circuit Design, 2017
Most DSP processors include one or more special AGUs that are dedicated to calculating addresses. Manufacturers refer to these units by various names. For example, Analog Devices calls its AGU a data address generator, and AT&T calls its AGU a control arithmetic unit. An AGU can perform one or more complex address calculations per instruction cycle without using the processor’s main data path. This allows address calculations to take place in parallel with arithmetic operations on data, improving processor performance. The differences among address generation units are manifested in the types of addressing modes provided and the capability and flexibility of each addressing mode. As an example, let us look at data address units in ADSP-21xx family.
A Bio-Inspired, Self-Healing, Resilient Architecture for Digital Instrumentation and Control Systems and Embedded Devices
Published in Nuclear Technology, 2018
Shawkat S. Khairullah, Carl R. Elks
In BioSymPLe each one of the three cells—B cell, T cell, and stem cell—has a similar internal structure, which is shown in Fig. 4. However, their functionalities are different and are based on the genetic codes stored in the configuration memory. The basic structure of the cell is comprised of two partitions: data flow and control flow. Data flow includes the data path for the adaptive functional block (AFB) unit, I/O routing direct unit, and I/O routing diagonal unit to make each cell capable of being connected to its neighboring cells from north, south, east, and west. The control flow embeds an address generation unit to store the address of the cell, a configuration memory that stores the next address of each cell and the genetic codes that configure both the execution unit and the two routing units, and a fault confinement unit to disconnect the faulty cell from its neighboring cells in case a permanent fault occurs inside the 1131 data path or the LUT data path.
Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications
Published in International Journal of Electronics, 2019
Venkata Rao Tirumalasetty, Madhusudhan Reddy Machupalli
Adder is one of the most important components of a CPU (central processing unit), arithmetic logic unit (ALU), floating-point units and an address generation unit such as cache or memory access unit. It is extensively used in many VLSI systems such as application-specific DSP architectures and microprocessors (Rabey, Chandrakasan, & Nikolic, 2011). In addition to its main task, that is, adding two binary numbers, has been the most important block involving multiple operations such as subtraction, multiplication, division, calculation of addresses, and so on. In most of these systems, the adder is a part of the Critique that determines the overall performance of the system. Therefore, improving the performance of the 1-bit adder cell is an important goal.