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Microprocessors and Microcontrollers: Past, Present, and Future
Published in Wasim Ahmed Khan, Ghulam Abbas, Khalid Rahman, Ghulam Hussain, Cedric Aimal Edwin, Functional Reverse Engineering of Machine Tools, 2019
Abdul Haseeb, Muhammad Faizan, Muhammad Faisal Khan, Muhammad Talha Iqrar
The bits of microprocessor/microcontroller define the internal data bus of microprocessor which means the size of data transfer and manipulation in one clock cycle. They also define the internal registers and memory storage. An 8-bit microcontroller is a low-cost controller, designed for projects having single operation, while a 16-bit controller is just like 8-bit controller but has more precision of arithmetic calculation. A 32-bit controller is a high-performance and relatively high-cost controller having high precision in arithmetic calculation and can interface large memories. 32-bit and 64-bit microcontrollers are generally used in multitasking applications and are capable of running operating system. With the increase in the bits of microcontroller, the performance enhances with increase in cost. Generally, a low-performance microcontroller is used for devices with less critical task and low-cost design. 32-bit and 64-bit microcontrollers are high-performance microcontrollers with relatively high cost and give performance like PCs such as multitasking, multimedia interfacing, and Internet connectivity.
M
Published in Splinter Robert, Illustrated Encyclopedia of Applied and Engineering Physics, 2017
[electronics, general] Integrated circuit used for performing computational algorithms. Semiconductor chip containing a central processing unit (CPU) electronic circuit configuration. The first microprocessor was introduced in 1974 by the Intel® Corporation (founded in 1968) with 8-bit capability, leading to the rapid reduction in the size of the computer to a portable device. The microprocessor forms the heart of every modern day computer and control unit. Microprocessors provide the logic for most digital devices, ranging from fuel injection to nuclear power plant temperature regulation. The microprocessor is designed with a specific clock speed, well in excess of 2.4 GHz at the time of this work, indicating the number of calculations that can be performed per second. Next to the processor speed, a microprocessor is classified by the bandwidth of the signal; 8−, 16−, 32−, 64−, or 128-bit (not common in personal computers [PCs]). The processor’s “bit” parameter refers to the magnitude of the data types that the processor can handle next to the size of its registry. A 64-bit processor has the capability of storing 264 computational values, where the data are also temporarily stored in memory addresses. The 64-bit CPU is hence capable of accessing over 109 times as much physical memory in comparison to a 32-bit processor (see Figure M.99).
Introduction to computer architecture
Published in Joseph D. Dumas, Computer Architecture, 2016
The increase in main memory sizes for all sorts of systems from personal computers to servers and mainframes helped bring 64-bit CPUs (and operating systems) to the forefront during the sixth generation of computing systems. Although 64-bit supercomputer architectures debuted during the fourth generation and 64-bit servers began to appear during the fifth, it wasn’t until 2003–2004 that first AMD and then Intel produced 64-bit versions of their ubiquitous x86 processors. In April 2005, Microsoft released a 64-bit version of its Windows XP Professional operating system, following up in January 2007 with 64-bit Windows Vista. These and subsequent operating systems would take advantage of the newest processors with their AMD64 and Intel 64 architectures, generically known in the industry as x86-64. While previous PCs and servers running 32-bit operating systems could only address 232 bytes (4 gigabytes) of main memory, it henceforth became common for even inexpensive desktop and laptop systems to exceed that amount. Theoretically, 64-bit systems could address up to 264 bytes (16 exabytes) of memory space, although (as of this writing) current implementations only use 48 of the 64 possible address bits for a total available memory space of 256 terabytes.
The effects of a standard elliptical vs. a modified elliptical with a converging footpath on lower limb kinematics and muscle activity
Published in Journal of Sports Sciences, 2020
Erik Hummer, Eryn Murphy, David N. Suprak, Lorrie Brilla, Jun G. San Juan
A wireless electromyography system (Noraxon DTS, Scottsdale, Arizona, USA) was utilized to measure muscle activity of the following muscles on the right side: GM, VL, and VM. Muscles were palpated using submaximal contractions to identify the muscle belly, upon which electrodes were placed in line with the muscle fibres (Rainoldi et al., 2004). The same investigator placed all EMG surface electrodes for each participant to ensure similar placement between participants. Sampling frequency was set to 1500 Hz with a gain of 500 prior to acquisition using an amplifier and CMRR > 100 dB. Electromyography data were transmitted via Bluetooth to a 64-bit computer system. Disposable self-adhesive Ag/AgCl dual snap surface electrodes with an inter-electrode distance of 1.75 cm were placed on the muscle bellies in line with the muscle fibres of each muscle.
Performance enhancement of multivariable model reference optimal adaptive motor speed controller using error-dependent hyperbolic gain functions
Published in Automatika, 2020
Omer Saleem, Mohsin Rizwan, Khalid Mahmood-ul-Hasan, Muaaz Ahmad
The fixed-gain LQI controller lacks robustness against the influences of modelling errors caused by faulty identification, un-modelled intrinsic nonlinearities, or environmental indeterminacies. Thus, it is retrofitted with a stable online indirect MRAS [33]. The MRAS adaptively modulates the state-feedback gains, as a function of the gradient of error between the actual closed-loop system and reference system, after every sampling interval [34]. The adaptive self-tuning of state-feedback gains enhances the robustness of the system. It renders a significant improvement in the system’s error-convergence rate while eliminating fluctuations and overshoots (or undershoots), even in the presence of bounded exogenous disturbances and parametric uncertainties. The reference model is implemented in a 64-bit computer. It functions concurrently with the actual system and generates control decisions based on the actual state-feedback. The derivation of the proposed model-reference Adaptive LQI (ALQI) controller is presented as follows [28]. Consider the linear system described by (14). The objective is to construct a stable control law such that the response of the controlled system imitates that of the reference system, given by (15).
LFSS-KF: lightweight fast real-time security standards with key fusion for surveillance videos
Published in The Imaging Science Journal, 2022
Chandan Kumar, Shailendra Singh
In the literature, there is a wide range of picture encryption methodologies. The Secure IOT (SIT) [30] and Secure Force (SF) [31] techniques are the most popular. IoT-based surveillance programmes must meet basic security criteria to preserve video data. According to Xing Zhang et al. [32], a lightweight encryption mechanism is defined in the context of layered cellular automata (LCA). Our methodology accounts for the deleted incentives for money invested in the underlying sickness of eight-layer cell automata (CA), which itself is formed by randomly determined rules for the LCA’s phase advances. As a result, all returns on starting capital are encoded at the same time and in the same manner. On the security camera, Xing Zhang’s encoded rewards on initial investment are saved and can be retrieved by confirmed clients on demand. Without obtaining a return on their investment, any client on the internet can watch the reconnaissance video eternally. As a result, according to hypothetical investigations and studies, this work is expected to develop and investigate both proficient and successful encryption for VS. Muhammad Usman et al. [30] proposed Secure IOT as a lightweight encryption approach (SIT). It is a 64-bit based block cipher that uses a 64-bit key to encrypt data. The architecture of the algorithm is a combination of Feistel and homogeneous substitution-permutation networks. According to simulations, the technique provides significant security for just five encryption cycles. The technique is conveniently implemented onto the hardware using a low-cost 8-bit microcontroller, and the results are also compared with the encryption standards in terms of the code size, memory usage and encryption/decryption execution cycles. Fedorov et al. [33] devised an optical flow-based motion estimate method for analysing traffic flow using video analysis.