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Interfacing Personal Computers
Published in Zdravko Karakehayov, Knud Smed Christensen, Ole Winther, Embedded Systems Design with 8051 Microcontrollers, 2018
Zdravko Karakehayov, Knud Smed Christensen, Ole Winther
The UART’s FIFO buffers can be viewed as a mail box at the lowest hierarchical level in the serial communication. Usually, a bigger buffer is organized in the PC memory. A popular scheme is the ring or circular buffer. Figure 6.14 illustrates the operation of an example ring buffer. In fact, it is a receive ring buffer which we use in the following version of the terminal emulator program. We allocate an area in the memory with a start address rec_buffer. The number of the memory locations is BUFFER_SIZE. The actual size of the buffer is BUFFER_SIZE – 1. The ring buffer is manipulated by a write pointer ptr_w and a read pointer ptr_r. The used memory from the ring buffer appears shaded in Figure 6.14. Normally, an interrupt handler reads the characters from the UART and writes them to the ring buffer. Tasks from the main program can read characters from the ring buffer. In the current implementation, if the ring buffer becomes full, the incoming characters are not written until free space is available again.
Auxiliary Storage
Published in Subrata Ray, Fortran 2018 with Parallel Programming, 2019
The processor allocates an identifier id to the integer variable, which may subsequently be used to test the status of the asynchronous data transfer using the pending specifier. IOMSG=char-variable (read, write), IOSTAT=integer-variable (read, write), PAD=char-string (read), ROUND=char-string (read, write), SIGN=char-string (write), SIZE=integer (read): These have already been discussed.POS=integer (read, write)
Efficient and Low-Power NoC Router Architecture
Published in Choi Jung Han, Iniewski Krzysztof, High-Speed and Lower Power Technologies, 2018
The flit arrival/departure of a dynamic input-port can be easily compared with the static VC input-ports. Figure 9.2 shows the architectures of these input-ports. The control logic of the static input-port is simpler, where each VC can be configured by using a parallel FIFO buffer, as shown in Figure 9.2a [7]. The number of VCs is equal to the number of FIFOs, as each FIFO represents a VC. The read-pointer and the write-pointer point to the location of a FIFO, whe re a flit is read or written, respectively. A pointer works like a simple counter, which is incremented circularly and continuously for each read and write operation. The flit arrival/departure is also simpler in a static input-port. If arbitration takes one step, the arrival/departure of flits in a squeezed pipelined scheme consumes two clock edges, as illustrated in Figure 9.3a. At the entrance of an input-port, the arriving flit is decoded according to its VC-ID (VC identification) and by means of the first de-multiplexer. Then it waits to be latched in the FIFO buffer (VC) before the first clock edge. At the first clock edge, the flit is stored in the VC where a request corresponding to that flit is simultaneously issued to the arbiter. At the second clock edge, the arbiter allocates the address for the crossbar switch (output) and ID for the downstream router VC, then issues a grant signal. The grant signal causes the flit to travel out of the router. For proper operation of the decoder at the entrance of the input-port, the VC-ID should be issued before latching the flit in the buffer. Assuming that the flit and its VC-ID are transferred at the same clock transition, each flit arrival/departure requires a two-clock event delay in the static router. We have assumed that the FIFOs are dual-port, where the arrival of one flit can coincide with the departure of another flit.
Single-Ended 8T SRAM cell with high SNM and low power/energy consumption
Published in International Journal of Electronics, 2022
Javad Mohagheghi, Behzad Ebrahimi, Pooya Torkzadeh
where read SNM and hold SNM are the static noise margins during the read and hold operations. Write SNM is the write margin of the cell. Read delay is the read access time. Pleakage is the average leakage power. Pread and Pwrite are dynamic powers of the cell during the read and write operations, respectively. The area used here is the bit-cell area normalised to the 6T SRAM cell. Table 7 lists the EQM of SRAM cells considered in this work at different supply voltages. We observe that the proposed 8T SRAM cell has the highest EQM at all supply voltages. The EQM of the proposed 8T SRAM cell, at a supply voltage of 0.5 V, is 84x, 12.4x, 45.8x, 5x, 37.7x and 3.8x compared to the cells 6T, WRE8T, ST-1, SB9T, 12T, and 11T respectively. Therefore, the proposed 8T SRAM cell is an attractive choice considering the overall performance along with the least area overhead.
Hybrid buffers based coarse-grained power gated network on chip router microarchitecture
Published in International Journal of Electronics, 2020
Yogendra Gupta, Lava Bhargava, Ashish Sharma, M.S. Gaur
The hybrid design focus to maximize the advantages of emerging memory technologies for performance improvement with the same power budget. STT-MRAM has a higher density that inspires to incorporate greater buffer memory space as compared to SRAM under the same area constraint. We have seen already the effect of the virtual channels on the network performance. It boosts overall network performance with no additional area overheads. We took this hybrid buffer architecture from the literature ‘(Jang et al., 2012)’. Figure 9 represents the hybrid input buffer of a Virtual Channel. Compared to the pure SRAM buffer the STT-MRAM is attached to each Virtual Channel in parallel with the SRAM buffer. The First In First Out (FIFO) buffer control the ‘read/write’ pointer. Write pointer is pointing to SRAM buffer only because whenever a flit comes it first written into the SRAM buffer. The read buffer covers the entire buffer entries because the outgoing flit can depart either from STT-MRAM or SARM. The migration controller tracks the flit activity and relocate the flit from STT-MRAM to SRAM. We have used the power efficient ‘lazy migration’ scheme ‘(Jang et al., 2012)’.
A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation
Published in International Journal of Electronics, 2022
Jiaxun Lv, Zilin Wang, Maohang Huang, Yajuan He
The write/read power is defined as the power consumption of SRAM during write/read operations. As shown in Tables 3, 7T and 8T cells have relatively smaller read power consumption due to its less number of switched control signals and bit-lines. DA-9T, TG-9T, and SPG-11T SRAM cells have larger read power consumption due to the VVSS structure, which needs to be discharged before read operation and results in extra power consumption. The proposed 9T cell has the moderate read power, because 1T read path has relatively larger read current which results in larger read power than that of 8T cell. At a 0.5 V supply voltage, the read power consumption of our proposed 9T is 1.21× compared with 8T SRAM cell.