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Advanced Research in On-Chip Optical Interconnects
Published in Christian Piguet, Low-Power CMOS Circuits, 2018
Ian O′Connor, Frédéric Gaffiot
A promising approach to the interconnect problem is the use of an optical interconnect layer. Such a layer could empower an enormous bandwidth increase, immunity to electromagnetic noise, a decrease in the power consumption, synchronous operation within the circuit and with other circuits, and reduced immunity to temperature variations. Important constraints when developing the optical interconnect layer are the fact that all fabrication steps have to be compatible with future IC technology and that the additional cost incurred remains affordable. Difficulties expected are obtaining a large enough optical-electrical conversion efficiency, reducing the optical transmission losses while allowing for a sufficient density of photonic waveguides on the circuit and reduction of the latency while operating above the 10-GHz mark. Sections 5.3, 5.4, and 5.5 describe, respectively, the issues involved in photonic waveguides, active devices, and optoelectronic conversion circuits.
Paradigm Shift of On-Chip Interconnects from Electrical to Optical
Published in Thomas Noulis, Noise Coupling in System-on-Chip, 2018
Swati Joshi, Amit Kumar, Brajesh Kumar Kaushik
In modern day very-large-scale integration (VLSI) chips, the complexity due to dense interconnects and a high data transmission rate presents several communication problems within the integrated circuit. The interconnect technologies are not able to keep up with the performance expected from high-performance computing systems and microprocessor chips at further scaled technology nodes. This is a critical factor in the design of high-performance electronic systems. The international technology roadmap for semiconductors (ITRS) has highlighted the existence of interconnect problems with scaling [1]. The fundamental paradigm shift takes place when shifting to quantum concepts from conventional laws of governing and explaining the behavior of interconnects. For VLSI and ultra-large-scale integration (ULSI) circuits, ITRS reports suggest that there will be a material limit imposed by conventional metal interconnects beyond a technology node of 8 nm. Thus, once we reach this limit, different materials, techniques, and technologies would have to be explored that can offer the projected performance requirements compatibility with existing CMOS technology. Several emerging technologies, such as carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), have been given extensive importance by researchers to meet chip performance in deep sub-micrometer and nanometer regimes. Being reliable and economical, on-chip communication is currently monopolized by electrical interconnections, however, optical interconnects dominate long distance communication due to their high bandwidth and low signal attenuation.
Prospects of surface emitting lasers
Published in Jong-Chun Woo, Yoon Soo Park, Compound Semiconductors 1995, 2020
By taking the advantage of wide band and small volume transmission capability, the optical interconnect is considered to be inevitable in the computer technology. Some parallel interconnect scheme is wanted and new concepts is being researched as shown in Fig. 6. Vertical optical interconnect of LSI chips and circuit boards may be another interesting issue. In any way, the two-dimensional arrayed configuration of surface emitting lasers and planar optics will open up a new era of optoelectronics. A new architecture for 64 channel interconnect has been proposed and a modeling experiment was performed using GaAlAs VCSEL arrays.
Reliability of vertical-cavity surface-emitting laser arrays with redundancy
Published in Automatika, 2021
The expected demand in data transmission bandwidth growth today places increasingly difficult requirements on the density, thermal management, and cost of components in data centres where the processing of aggregate data transfer is presently exceeding petabytes/sec. The existing technologies and technologies being developed to address this demand are progressively more relying on optical interconnects in place of copper due to the promise of lower power consumption and price, yet data-centres still require lower cost, power dissipation and size of interconnect components. Today, the cost of transceiver manufacturing is limited by packaging cost and yield, rather than electronic or optical components. Vertical-cavity surface-emitting laser (VCSEL) based technologies are preferred in environments where low power consumption and high density are of primary interest. Presently, VCSELs driven by SiGe driver circuitry operate line rates above 50 Gb/s [1]. Silicon and silica-based packaging platforms offer flexibility in materials choices, 3D-micromachining using standard semiconductor processes on a wafer level [2].