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Power–Performance Trade-Offs in Design of SoCs
Published in Christian Piguet, Low-Power Processors and Systems on Chips, 2018
Victor Zyuban, Philip Strenski
Changing the processor architecture is another way to make trade-offs between performance and energy. Architectures that are more complex deliver higher architectural performance or instructions per cycle (IPC), but inevitably dissipate more energy per every executed instruction. Similar to building the optimal energy-delay curve in the circuit domain, an optimal energy-delay curve can be constructed in the architectural domain, as an envelope in the power–performance space of all feasible architectural alternatives [20]. Similar to Equation (10.1), the architectural complexity ξ can be defined as⋆ () ξ=−D∂EE∂D|fixedη,vorξ=−%E%D|throughar chitecture
Core-Based Parallelism
Published in Heqing Zhu, Data Plane Development Kit (DPDK), 2020
Qun Wan, Heqing Zhu, Zhihong Wang
Inside each CPU core, hardware-based execution parallelism such as instruction-level parallelization (ILP) and SIMD helps the software performance. IPC is an important indicator to measure the software efficiency. Linux “Perf” is a software utility that can profile and measure how applications perform. The above example indicates “IPC = 0.84”. In the sample of Skylake processor, four execution units are available, thus limiting the upper bound of “IPC = 4”. The higher IPC, the more efficiently software is designed (Figure 3.7).
Processor Physics and Moore’s Law
Published in Vivek Kale, Parallel Computing Architectures and APIs, 2019
If the system completes C programs during an observation period of T seconds, its throughput X is measured as C/T programs/seconds. For processors, a more commonly used throughput measure is the number of instructions executed in a clock cycle, referred to as its instructions per cycle (IPC). Power consumptionPower is an important issue because it directly translates into heat production. Most integrated circuits will fail to work correctly if the temperature rises beyond a few degrees. Power consumption has two components: Dynamic power consumption relates to power consumed when there is switching activity (or change of state) in a system. Dynamic power is directly proportional to the extent of switching activity in the system and the clock frequency of operation. It is also proportional to the capacitance in the circuits and wires, and to the square of the supply voltage of the circuits.Static power consumption relates to power consumed even when there is no switching activity in the system. Static power consumption occurs due to leakage currents in the system. With continued scaling in transistor technology—reduction in transistor sizes—static power consumption is becoming comparable to dynamic power consumption. Static power consumption is also related to the supply voltage. Therefore, to develop low-power systems, computer hardware designers strive to reduce the supply voltage of the circuits as well as to reduce the amount of hardware complexity used to perform the required functionality.PriceAll things being equal, between two comparable computer systems, price will be an important factor. The major factors affecting the price areDesign costManufacturing costProfit marginAll of these are impacted by the sales volume. In general, price increases exponentially with the complexity of the system. Thus, it is imperative to reduce hardware complexity at all costs.SizeSize is an important design consideration, especially for laptops and embedded systems.
System performance enhancement with thread suspension for simultaneous multi-threading processors
Published in International Journal of Computers and Applications, 2020
For a multi-threaded workload, total combined Instruction Per Clock Cycle (IPC) is a typical indicator used to measure the overall performance, which is defined as the sum of each thread’s IPC: where N denotes the number of threads per mix in the system. However, in order to preclude starvation effect among threads, the so-called Harmonic IPC is also adopted, which reflects the degree of execution fairness among the threads, namely,