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Unified Computer Arithmetic for Handheld GPUs
Published in Krzysztof Iniewski, Circuits at the Nanoscale, 2018
Byeong-Gyu Nam, Hyejung Kim, Hoi-Jun Yoo
Since the 3D computer graphics is extremely compute-intensive and data-parallel application, the GPUs adopt highly data-parallel architecture with single instruction multiple data (SIMD) arithmetic units. The GPU architecture is composed of the geometry and rendering pipeline stages as shown in Figure 27.4. It has fixed-function rasterizer, frame buffer operation unit, and two programmable stages incorporating the vertex and pixel shaders in geometry and rendering stages, respectively. The rasterizer interfaces the vertex and pixel shaders by setting up triangle parameters. The frame buffer unit processes several frame buffer operations like depth test and pixel-level blending operations. Basically, the programmable shaders are stream processors and they can substitute certain stages of graphics pipeline by assembly programming of its instructions. They have two main functional units, a four-way vector SIMD unit for vector multiplication and dot product and an elementary function unit for the functions like reciprocal and exponential functions as depicted in Figure 27.5.
Preliminaries
Published in Wong Gabriyel, Wang Jianliang, Real-Time Rendering: Computer Graphics with Control Engineering, 2017
In the course of rendering a 3D scene, many inputs and settings such as the geometries of 3D objects and their material “look” parameters are sent to the graphics hardware for processing. About a decade ago, outdated graphics hardware relied solely on a few hard-wired algorithms to process such data via a method known as the fixed function rendering pipeline. As a result, real-time rendering application developers had little space to control the look of a 3D object based on a limited set of functions that computed the rendering output. The impact of such limitations is the lower quality of imagery generated from computer graphics hardware.
Fast and cross-vendor OpenCL-based implementation for voxelization of triangular mesh models
Published in Computer-Aided Design and Applications, 2018
Mohammadreza Faieghi, O. Remus Tutunea-Fatan, Roy Eagleson
To accelerate voxelization, some of the prior studies have involved the graphics pipeline for parallelization of the voxelization in rendering passes [4-7],[9]. Nevertheless, the point sampling method used by the conventional rasterizers of the pipeline is known to cause inaccurate voxelizations for thin structures. To address this, [22] proposed a “conservative voxelization” technique that in turn introduced redundant voxels, an issue that was later rectified in [8] by means of hardware-based tessellation and point-based rendering. Even though the latter technique is faster by two orders of magnitude, the fixed-function tesselator of the pipeline was found to introduce inaccurate results such that while the involvement of the graphics pipeline might be sufficient for real-time voxelization, its limited flexibility might be responsible for inaccurate results.