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Introduction
Published in Heqing Zhu, Data Plane Development Kit (DPDK), 2020
The line rate (transmitting in the wire speed) is the maximum packet (or frame) forward rate, which is limited by the speed of physical interface, theoretically. Take Ethernet as an example. The interface is defined as 1 Gbps, 10 Gbps, 25 Gbps, 40 Gbps, and 100 Gbps; each represents the maximum transmission rate, measured in bps. Indeed, not every bit is used to transmit the effective data. There is an inter-packet gap (IPG) between Ethernet frames. The default IPG is 12 bytes. Each frame also has a 7-byte preamble and a 1-byte Ethernet start frame delimiter (SFD). The Ethernet frame format is shown in Figure 1.7. The effective data in Ethernet frame mainly includes the destination MAC (media access control) address, source MAC address, Ethernet type, and payload. The packet tail is known as FCS (frame checksum) code, which is designed to validate the Ethernet frame integrity (Figure 1.7).
Ethernet
Published in Vikas Kumar Jha, Bishwajeet Pandey, Ciro Rodriguez Rodriguez, Network Evolution and Applications, 2023
Vikas Kumar Jha, Bishwajeet Pandey, Ciro Rodriguez Rodriguez
Multicasting is an efficient Ethernet delivery mechanism while sending the same Ethernet frame to multiple recipients of Ethernet. The same Ethernet frame can be received by a group of stations by using a multicast addressing. This will require a multicast group to be configured with a specific multicast address for a set of stations to receive particular frame. Data sent with the multicast address as the destination address in the frame will be received by all stations in the multicast group.
Ethernet and Ethernet/IP
Published in Sunit Kumar Sen, Fieldbus and Networking in Process Automation, 2014
The maximum payload of an Ethernet frame is 1500 bytes. It takes about 122 µs for the frame to complete its transmission. This time is quite high and is likely to congest the transmission medium such that any time critical data will fail to achieve determinism. A way out to achieve determinism is to prioritize such time critical data to have the right of way as far as transmission of data is concerned. This technique is called message prioritization, also called QoS.
Ethernet-Based Servo-Hydraulic Real-Time Controller and DAQ at ELSA for Large Scale Experiments
Published in Journal of Earthquake Engineering, 2022
Marco Peroni, Pierre Pegon, Francisco Javier Molina, Philippe Buchet
The different slaves are connected among themselves and/or the Master Control Unit simply with two cables: an industrial robust and shielded EtherCAT® bus and a power supply cable creating the control network. At this point, it is worth remembering that EtherCAT® passes the Ethernet frame sent by the EtherCAT® master through all EtherCAT® slave nodes rather than sending specific frames data to each of them. The master is the only device in an EtherCAT® network that is allowed to send new frames. Each slave only reads and writes the data addressed to it in a specific area within the frame before transmitting the frame to the next slave in few nanoseconds. The frame is then sent back by the last slave and returns to the master after passing through all slaves again. The bandwidth is dramatically improved since one Ethernet frame per cycle is generally sufficient for sending and/or getting all the slave data.
Modelling and temporal evaluation of networked control systems using timed automata with guards and (max,+) algebra
Published in International Journal of Systems Science, 2018
When receiving a read request from a communication processor in Remote_module_stack (assuming the stack is empty), the RIOM takes the value that is available in Input_in_remote_module and prepares to transmit it to the controller that was requesting it via the network. The response must indeed be contained in a Modbus frame, which in turn is also contained in an Ethernet frame. It is this double packing that takes up most of the processing time in RIOM. The response is transmitted at the end of the treatment.
Design and FPGA based Implementation of IEEE 1588 Precision Time Protocol for Synchronisation in Distributed IoT Applications
Published in Australian Journal of Electrical and Electronics Engineering, 2022
Aamir Sohail Nagra, Irfan Allahi, Muhammad Adeel Pasha, Shahid Masud
Hardware time stamps are obtained using an IEEE 1588 PTP IP core implemented in Verilog. For packet frames, a dummy Ethernet Traffic Generator is used which includes all the necessary headers for the Ethernet frame, and the rest of the data is generated using incremental counter values.