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Published in Philip A. Laplante, Comprehensive Dictionary of Electrical Engineering, 2018
memory address register (MAR) a register inside the CPU that holds the address of the memory location being accessed while the access is taking place. memory alignment matching data to the physical characteristics of the computer memory. Computer memory is generally addressed in bytes, while memories handle data in units of 4, 8, or 16 bytes. If the "memory width" is 64 bits, then reading or writing an 8 byte (64 bit) quantity is more efficient if data words are aligned to the 64 bit words of the physical memory. Data that is not aligned may require more memory accesses and more-or-less complex masking and shifting, all of which slow the operations. Some computers insist that operands be properly aligned, often raising an exception or interrupt on unaligned addresses. Others allow unaligned data, but at the cost of lower performance. memory allocation the act of reserving memory for a particular process. memory bandwidth the maximum amount of data per unit time that can be transferred between a processor and memory. memory bank a subdivision of memory that can be accessed independently of (and often in parallel with) other memory banks. memory bank conflict conflict when multiple memory accesses are issued to the same memory bank, leading to additional buffer delay for such accesses that reach the memory bank while it is busy serving a previous access. See also interleaved memory. memory block contiguous unit of data that is transferred between two adjacent levels of a memory hierarchy. The size of a block will vary according to the distance from the CPU, increasing as levels get farther from the CPU, in order to make transfers efficient.
Peer reviewer training to build capacity in engineering education research
Published in Australasian Journal of Engineering Education, 2023
Kelsey Watts, Randi Sims, Evan Ko, Karin Jensen, Rebecca Bates, Gary Lichtenstein, Lisa Benson
In contrast, upon completion of the programme, the Post-SPRs show that mentees identify shared criteria and are more aligned with mentors. In their responses to the Post-SPR for both manuscripts, mentees aligned at least 50% of the time on five codes for both cohorts 1 and 2. Similarly, mentors aligned at least 50% of the time on four codes for both cohorts 1 and 2 in their responses to the Post-SPR. Of these four aligned codes for the mentors, mentees aligned with three of them (E-3P, C-2N, and C-4N). This alignment in codes after participation in the programme was consistent for the two different manuscripts used for training and evaluation purposes in this study. This provides evidence that through participation in a mentored review programme, mentees were able to enhance their schema development and become more closely aligned with mentors.
Two-dimensional reinforcement of epoxy composites: alignment of multi-walled carbon nanotubes in two directions
Published in Advanced Composite Materials, 2020
Ehsan Moaseri, Mostafa Fotouhi, Behnaz Bazubandi, Majid Karimi, Majid Baniadam, Morteza Maghrebi
Figure 7(c) shows the 2-D aligned MWCNT-reinforced composites. Interestingly, considerable improvements were achieved compared to the randomly orientated MWCNT composite in both directions. At the same reinforcement load, the tensile strength of the composite was enhanced around 28% and 23% in the direction of the applied magnetic and electric fields, respectively. Hence, one can conclude that these two fields can successfully align MWCNTs along their field lines in the presence of the other field. Based on Figure 7(a,b), we can assume M-MWCNTs are only affected by the magnetic fieldas-received MWCNTs are only aligned along the electric field due to their low magnetic susceptibility.
Optimised memory allocation for less false abortion and better performance in hardware transactional memory
Published in International Journal of Parallel, Emergent and Distributed Systems, 2020
Hardware transactional memory is based on a cache line. Thus in the organisation of heap, we need to take special care of small memory allocations (objects smaller than 64 bytes). Our simple heap organisation is shown in Figure 4. In our memory allocator, we first prepare a special large amount of memory (the super block in Figure 4, we use map to allocate the super block from the operating system) and divide the super block into fixed 64 bytes small blocks. The super block is 64-byte-aligned thus each of the small 64 bytes block fits in a cache line. Each allocation which is smaller than 64 bytes can just get a small block from here. We keep the freed blocks in a freelist to facilitate further allocation. In our mechanism the code in Figure 2(a) can transparently separate the arrays a and b in different cache lines (as shown in Figure 4) and thus we can solve the false abortion problem without altering the code.