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Power Grid Design
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
The power delivery system includes on-chip and off-chip power grid and decoupling capacitors on die, package, and board. The power grid (power distribution network) provides the Vdd and ground signals throughout a chip. Compared to signal wires, power wires typically have lower impedances to reduce power grid current resistance (IR) drops because of currents drawn by functional blocks. All levels of decoupling capacitors are extensively used to suppress transient noise because of the transient currents drawn by functional blocks and because of the interaction of package inductance and switching currents, also known as LdIdt noise or ΔI noise. The inductive components in package power grids and decoupling capacitors are the major limitation for performance at high frequency. Supply voltage variations can lead not only to problems related to spurious transitions but also to delay variations [2,3] and timing unpredictability [4]. Thus, a successful design requires careful design of all levels of the power delivery system.
Out-of-round railway wheels and polygonisation
Published in Vehicle System Dynamics, 2023
Simon Iwnicki, Jens C. O. Nielsen, Gongquan Tao
A hybrid approach to predict noise due to wheel–rail impact has been presented by Wu and Thompson [60]. In the first step, a time-domain model is applied to calculate the wheel–rail contact force. The time history of the impact load is then transformed to the frequency domain and converted into the form of an equivalent roughness spectrum that can be used as input for the prediction of noise in a conventional frequency-domain model. A similar approach focussing on ground-borne vibration generated by impact loading was presented in [115]. A next step to improve the understanding of wheel–rail impact noise is to develop a time-domain model for the prediction of transient noise, where the non-linear vehicle, track and wheel–rail contact models are extended to be accurate for frequencies up to 5 kHz.
Variation aware intuitive clock gating to mitigate on-chip power supply noise
Published in International Journal of Electronics, 2018
Alak Majumder, Pritam Bhattacharjee
One of the attempts to reduce transient noise (i.e. PSN) in silicon chip was done by generating variable clock (which was first introduced in 1989 (Branson, 1989)) using a digital controlled oscillator (DCO) in 2010 (Tierno et al., 2010), which got improvised in 2016 by replacing the DCO with a voltage controlled oscillator (Bhowmik, Deb, Pradhan, & Bhattacharyya, 2016). Subsequently in 2017, gating logic was employed in clock tree to control the current ramp to depict lower current drawn from the chip leading to reduced transient noise (Majumder, 2017). Another solution to this noise issue was to divide the system clock into multiple sub-clocks with correlative skew in order to reduce the peaks of dynamic current flow by a factor of two (Vittal, Ha, Brewer, & Marek-Sadowska, 1997).
Novel, low-supply, differential XOR/ XNOR with rail-to-rail swing, for hamming-code generation
Published in International Journal of Electronics Letters, 2018
Musala Sarada, Avireni Srinivasulu, Dipankar Pal
The width of transistors for all the proposed circuits is shown in Table 3. Length of all transistors is fixed at 90 nm. Transient, Noise and DC Monte Carlo analyses of all the proposed circuits are performed. To avoid redundancy, the results of only the design of Figure 5(c) are shown in below. Figure 11 shows the transient response for Monte Carlo analyses of 200 samples. It shows that the response is same for all samples. Histograms of two outputs are shown in Figures 12 and 13. These figures show that maximum number of samples is appearing at required output value, which is the desired outcome to prove robustness of the proposed designs. Noise-Monte Carlo analysis was performed by varying the temperature and DC supply. It is presented in Figure 14 (for XNOR output) where supply voltage as a component parameter of VDC is varied, and in Figure 15 (for XOR output) where variation with respect to temperature is shown. The corresponding responses for XOR and XNOR are similar and hence omitted.