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Design of a new carrier tracking loop in a positioning receiver
Published in Lin Liu, Automotive, Mechanical and Electrical Engineering, 2017
Zhongliang Deng, Shu Jiang, Jun Mo, Shengchang Yu
The carrier tracking loop is designed to accurately track the signal and is used to generate accurate local carriers, and finally to strip the carrier from the signal. The tracking loop is typically implemented by a Frequency-Locked Loop (FLL) and Phase-Locked Loop (PLL). The performance of the frequency-locked loop is equivalent to the performance of a high-order phase-locked loop, but the tracking precision is not as good as the phase-locked loop. The PLL has good noise immunity and high tracking accuracy under low dynamic conditions. However, if the Doppler shift is serious, and if the carrier is to be traced stably, the loop bandwidth needs to be amplified, which means more noise is entered, thus reducing the tracking accuracy.
Laser Velocimetry
Published in Richard J. Goldstein, Fluid Mechanics Measurements, 2017
Frequency trackers measure the instantaneous frequency Φ˙D of the LDV signal. The main types of trackers used in LDV are the phase-locked loop (PLL) and the frequency-locked loop (FLL), both of which are analog devices. These instruments work best when the signal is continuous (HBD), but they also work with LBD signals, provided that the time between bursts is not too long. Most commercial frequency trackers hold the value of the velocity measured from the last burst until a new measurement is achieved.
Analogue modulation theory
Published in J. Dunlop, D. G. Smith, Telecommunications Engineering, 2017
The analysis presented above deals only with the steady-state response of the PLL the assumption being that the loop is locked. If this is not the case the PLL will behave as a negative feedback system with the usual transient properties. The transient response of the phase locked loop is an important consideration as it determines the range of frequencies over which the loop will acquire lock and also the range of frequencies over which a frequency locked loop will remain in lock. The transient response of the phase locked loop depends on the frequency response of the loop filter and when H(f) = 1 the circuit is known as a first-order phase locked loop.
Control of three wire DSTATCOM using cascaded delayed signal cancellation effect
Published in Energy Sources, Part A: Recovery, Utilization, and Environmental Effects, 2021
Jayadeep Srikakolapu, Sabha Raj Arya, Rakesh Maurya
In-loop filter-type PLL: quasi type-I PLL falls in this category; the dynamic response is improved (Golestan et al. 2014). The prefilter type of PLLs is chosen as in-loop filter-type PLL suffers with stability and dynamic behavior (Ramezani et al. 2018). Further prefilter-type PLLs can be sorted as feedback, delay signal type, and filtering type (Katana and Bhimasingu 2018). A better transient response can be expected in feed-type PLL (Popadic et al. 2017). The feedback-type PLL like Discrete Fourier Transform (DFT) type and Weighted Least Square Error (WLSE) are powerful methods but complicated implementation is expected (Komarska, Janik, and Peroutka 2013). The dq frame and αβ frame are used majorly in filtering-type PLL. Moving Average (MA-PLL), Multiple Synchronous Reference Frame (MSRF-PLL), and Adaptive Synchronous Reference Frame (ASRF-PLL) are some types of dq-dependent PLLs. In this type of PLLs Stability is affected by the loop gain. Second-Order Generalized Integrator (SOGI PLL) is an observer type of αβ-based PLLs. Harmonic rejection capability is one of the drawbacks of such PLLs (Ali et al. 2018). In delay-based PLLs merits like mitigation of specific harmonics and better transient response are observed as in CDSC PLL (Wang, Etemadi, and Doroslovacki 2019). Inspired by the Generalized Delayed Signal Cancellation (GDSC) PLL used in (Golestan et al. 2016) in which prefiltering stage is responsible for fundamental extraction. It faces stability issues due to its nonlinear structure. A Frequency Locked Loop (FLL) operates in a reference frame which is stationary and PLL operates in a reference frame which is rotating. Although both the locked loops attain dynamic response and exactness under distorted conditions FLL is computationally burden less to control algorithm. An effective and low-cost execution FLL, i.e. Cascaded αβ Delayed Signal Cancellation (Cαβ-DSCFLL) is coined in (Srikakolapu, Arya, and Maurya 2019), small-signal model is provided for the FLL structure through which gain estimation and stability analysis is made and the present work shows the extension of reference (Srikakolapu, Arya, and Maurya 2019) which has been authored by the same authors and it includes hardware implementation along with experimental results.