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Digital Filters
Published in Jerry C. Whitaker, Microelectronics, 2018
Jonathon A. Chambers, Sawasd Tantaratana, Bruce W. Bomar
Linear-phase FIR digital filters can generally be implemented with acceptable coefficient quantization sensitivity using the direct convolution sum method. When implemented in this way on a digital signal processor, fixed-point arithmetic is not only acceptable but may actually be preferable to floating-point arithmetic. Virtually all fixed-point digital signal processors accumulate a sum of products in a double-length accumulator. This means that only a single quantization is necessary to compute an output. Floating point arithmetic, on the other hand, requires a quantization after every multiply and after every add in the convolution summation. With 32-bit floating-point arithmetic these quantizations introduce a small enough error to be insignificant for most applications.
New Design Patterns for Time-Predictable Execution of Function Blocks
Published in Alois Zoitl, Thomas Strasser, Distributed Control Applications, 2017
Matthew M. Y. Kuo, Partha S. Roop
Real numbers can be represented in floating point or fixed-point representation. Floating point numbers are, in general, more popular because they are primitive data types in programming languages. However, extra care is required when using floating points in time-predictable systems. The programmer should first determine the precision of the floating point arithmetic unit (single or double) of the target platform. If the target platform does not include a floating point arithmetic unit or the programmer is required to use a precision beyond the hardware support, compilers will utilize software libraries to perform floating point computations. Generally, these software libraries are designed with average case execution in mind [13] and contain loops that are hard to bound statically. Therefore, such libraries are unsuitable for time-predictable systems. Instead, fixed-point arithmetic should be used when hardware support for floating point computation is limited or not available. Fixed-point arithmetic is essentially the manipulation of integer values. These are natively supported by most processor architectures.
DSP Technology
Published in Douglas Self, Audio Engineering Explained, 2012
Fixed -point arithmetic is called fixed-point because it has a fixed decimal point position and because the numbers have an implicit scale, depending on the range that must be represented. This scale must be tracked by the programmer when performing arithmetic on fixed-point numbers. Most DSPs use the fixed-point 2s-complement format, in which a positive number is represented as a simple binary value and a negative value is represented by inverting all the bits of the corresponding positive value and then adding 1. Assuming a 16-bit word, there are 216 = 65,536 possible combinations or values that can be represented which allows the representation of numbers ranging from the largest positive number of 215-1 = 32,767 to the smallest negative (e.g., most negative) number of -2 15 = -32,768.
Hardware design implementation issues of the estimator-based controller using FPGA
Published in International Journal of Electronics, 2019
Kanthimathi R., Kamala J., Jaibalaganesh T., Vasuhi S.
Improper bit sizing of the variables and coefficient leads to faulty output. Refinement of active disturbance rejection control and optimisation of FPGA hardware resources is explained (Stankovic et al., 2018). Fixed-point arithmetic operation is employed, with different integer word lengths and fractional word lengths. Different arithmetic operations are applied to reduce delay and area. Nema and Nema (2013) have discussed PID controller implementation using different types of additions. Minimum delay (87% less) has been observed while using carry increment adder compared with other topologies. Fargham (Sandhu, et al., 2017) implemented adaptive Kalman filter to estimate wheel speed and acceleration for each wheel. Replacing multiplications with shift operations, the total number of operations is reduced. Iplikci and Bahtiyar (2016) and Ma, Saeidi, and Kennel (2014) described the basic finite-state modern predictive control (MPC) for prediction and derivative calculation purposes. In Ma et al. (2014), MPC is combined with a pulse-width modulator for an effective cost function optimisation algorithm. MPC with constant switching frequency is implemented with parallel and pipeline processing techniques to reduce execution time.
On the use of Youla–Kucera parametrisation in adaptive active noise and vibration control – a review
Published in International Journal of Control, 2020
For IIR adaptive compensators, provided that the SPR condition is satisfied, the poles of the internal ‘positive’ loop will be asymptotically stable but they can be very close to the unit circle (they can be inside of a circle of radius 0.99999..). This may induce some numerical problems in practice (when using truncation or fixed point arithmetic).