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Low-Power Memory Design for IoT-Enabled Systems
Published in Suman Lata Tripathi, Parvej Ahmad Alvi, Umashankar Subramaniam, Electrical and Electronic Devices, Circuits and Materials, 2021
Shilpi Birla, Neha Singh, N. K. Shukla
Since high speed and power efficient SRAMs are required in IoT devices, various new ultra-low-power subthreshold SRAM memories and their architectures have been proposed. With CMOS technology, scaling down the supply voltage was the most popular method to improve the overall power consumption. However, scaling of the supply voltages in scaled devices has various limitations such as an increase in leakage current, and scaling the device beyond the nanometer regime increases the variation in threshold voltages, which leads to other problems. These process variations affect the performance of SRAMs, particularly the read and write stability, which degrades the performance of SRAMs. Most of the SRAM cells fail during read in ultra-low-power applications. Various methods such as the butterfly curve and N curves are used to find the stability of SRAM cells [18]. Researchers have started working on the subthreshold regime to make ultra-low-power SRAM cells where power and stability are the main concerns. To address these issues, several architectures of SRAM cells have been proposed using CMOS technology. The electronics market started considering the CMOS SRAM to be the stakeholder in the memory market. Due to the scaling quality of CMOS, SRAM was having its grip on the market for the last few decades. In the last few years, CMOS scaling is confined to a limit which raised various issues such as short-channel effects (SCEs) and threshold voltage variations. The CMOS limitations have led to alternative devices such as FinFET and other nano-scaled devices such as CNTFETs and TFETs.
Mechanical Properties of Smart Materials
Published in Yichun Zhou, Li Yang, Yongli Huang, Micro- and MacroMechanical Properties of Materials, 2013
Yichun Zhou, Li Yang, Yongli Huang
For example, Figures 10.35 and 10.36 give experimental test results of PZT-51 ferroelectric materials under the effect of electromechanical coupling. These are the ferroelectric hysteresis loops of the electric displacement D3 and electric field E3, and the butterfly curves of strain ε33 and the electric field E3. Figure 10.35a and b show these results under the effect of nonstress and the effect of stress. In Figures 10.35 and 10.36, it is obvious that the shape of the hysteresis loop and the butterfly curve change with compressive stress. When compressive stress increases, the remnant polarization of ferroelectric material PZT-51 was significantly reduced, the coercive electric field decreased, and the residual strain was significantly reduced. These experimental test results are in good agreement [42] with calculations of the mathematical model of electromechanical coupling.
SRAM The Benchmark of VLSI Technology
Published in Santosh K. Kurinec, Krzysztof Iniewski, Nanoscale Semiconductor Memories, 2017
A technique to further speed up the SNM calculation is to adopt a behavioral look-up table to replace the compact model in simulation. Since the I–V curves of numerous devices can be in-line measured, it is straightforward to build a look-up table including the statistics of the technology (e.g., the sigmas and correlations of different I–V points). The butterfly curve can be simulated using the table with linear interpolations. This approach not only dramatically increases the speed calculating the SNM but also greatly reduces the delay in constructing fully calibrated compact models such as BSIMs or PSP.
Process Corners Analysis of Data Retention Voltage (DRV) for 6T, 8T, and 10T SRAM Cells at 45 nm
Published in IETE Journal of Research, 2019
For ultra low power design, one of the simplest methods is to lower the supply voltage. For the realization of high performance SoC, dense SRAM is required. As we know, SRAM is mainly used for storing and modifying data. For preservation, SRAM is used in standby mode. So, it is very important for SRAM to have reliable data retention. DRV is the minimum supply voltage of SRAM for which the data can be preserved. As scaling goes on, the process variation effect becomes dominant, affecting the reliability of SRAM. So, it is very important to analyse this DRV in the presence of process variations for reliable preservation behaviour of SRAM. DRV can be estimated from the butterfly curve as shown in Figure 1. The minimum voltage, for which the butterfly curve can be obtained and static noise margin (SNM) is about to be equal to zero, i.e. very close to it, is defined to be the DRV [8].
Area efficient layout design of CMOS circuit for high-density ICs
Published in International Journal of Electronics, 2018
Vimal Kumar Mishra, R. K. Chauhan
The transient and DC analyses of the proposed TBRS FD-SOI MOS structure-based CMOS inverter circuit are very promising and therefore applied to the design of 6T SRAM cell. The static noise margin (SNM) is considered as a stability of any SRAM cell, which is defined as the highest DC margin for which the cell state does not flip during its access. SNM of a bit cell is derived from butterfly curve. Figure 9 shows the butterfly curve of SRAM cell which corresponds to an ideal circuit. The read SNM from both transfer characteristics is extracted by a square-fitting method that is the largest square to be fitted in between overlapped plot of inverter transfer characteristics and its inverse characteristics. The SNM of the proposed cell is obtained as 565 mV which is much better than any other cell designed at 50 nm gate length MOS device.
Single-Ended 8T SRAM cell with high SNM and low power/energy consumption
Published in International Journal of Electronics, 2022
Javad Mohagheghi, Behzad Ebrahimi, Pooya Torkzadeh
In the hold state, the butterfly curve method is also employed to assess hold stability as HSNM. The HSNM shows the amount of noise voltage on the storage nodes that the cell can tolerate, and the data of the cell remains unspoilt in the hold state (Guo et al., 2017). Figure 9(a) shows the HSNM of different structures for different supply voltages. As shown, HSNM also decreases as the supply voltage decreases. HSNM for the symmetric ST-1 is the highest because it uses the Schmitt-trigger inverters structure. The hold yields are shown in Figure 9(b). Most SRAM cells, including the proposed cell, have a high hold yield as the bitlines are isolated from storage nodes in the hold state.