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RISC Architecture
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
The major components of this single-IC microprocessor family include a register file of 32 GPRs, each having 32-bits, and the processing logic to perform the basic fixed-point arithmetic/logic functions using 32-bit operands. Floating-point operations are executed by an on-chip or off-chip FPU supported also by an optional floating-point co-processor obeying IEEE 754 standards. MIPS never impose any earmarking on any of the registers in the chip for any special purposes. As a result, the local/global variables and the input/output parameters can all be put in any of the registers for even faster execution. A unit called system control co-processor provides communications with external memory (both cache and main memory), and also an automatic address translation logic supported by special-purpose arithmetic circuits to perform address computations required to handle virtual memory system. MIPS uses a deeper instruction pipeline of five stages, compared to four stages used in its contemporary counterpart ordinary SPARC. Each instruction in the instruction set is of 32 bits and word-aligned. The address space is 232 bytes (4 gigabytes) and byte addressable, while the upper 2-gigabyte address space is reserved for the operating system. The memory can be configured either as big-endian or as little-endian by selecting a pin on the chip, thereby satisfying the users of both tents. The machine supports paged virtual memory management. In general, MIPS architecture has been built up using different trade-offs where more thrusts have been put on software that ultimately resulted in creating problems for the software designers, particularly in the optimization of compiler design. Still, it has been done only for the sake of making the hardware simpler with faster operation to realize enhanced performance.
Virtualization of the Architectural Components of a System-on-Chip
Published in Lev Kirischian, Reconfigurable Computing Systems Engineering, 2017
The mechanism for the aforementioned implementation is the FPU. The FPU was defined as function-specific processing circuit performing: (1) data receiving and/or buffering, (2) data-execution according to the algorithm of a given function and an associated data structure, and (3) storage/transmission/outputting the result(s).
™ floating-point unit (FPU)
Published in Ying Bai, Microcontroller Engineering with MSP432, 2016
The behavior of the FPU can also be adjusted and specified to the different formats, such as the half-precision and single-precision floating-point values, the handle of NaN values, the flush-to-zero mode that sacrifices the full IEEE 754 compliance for execution speed, and the rounding mode for results.
Optimised Floating Point FFT Core for Improved OMP CS System
Published in International Journal of Electronics, 2022
Alahari Radhika, K. Satya Prasad, K. Kishan Rao
Here the hardware fusion-driven method and the canonical sign digitally driven change accumulation based Mantissa computing technique are used to reduce the numerical complexity occurring in the complex FFT calculation floating point arithmetically. By using the FFT butterfly layout hardware sharing redundant functions, the device performance overhead is reduced substantially. It is also shown that multiplier less FPU multiplication mantissa calculation contributes to a considerable reduction in complexity. Eventually, the metrics in twiddle-factor optimised FFT architecture of the two models of arithmetic optimisation are reinforced. The interrelationship of hardware and twiddle factor optimisation techniques within FPGA floating point units and output metrics has been precisely studied, and FPGA hardware syntheses for qualitative and quantitative measurements are implemented.
Effect of sequential pretreatment combinations on the composition and enzymatic hydrolysis of hazelnut shells
Published in Preparative Biochemistry & Biotechnology, 2021
Emir Zafer Hoşgün, Suzan Biran Ay, Berrin Bozan
The enzymatic hydrolysis of hazelnut shells was conducted in stoppered 50-mL conical flasks. The working solution of 20 mL was prepared by addition of cellulase (60 FPU/g dry biomass) and β-glucosidase (40 CBU/g dry biomass) in sodium acetate buffer (pH = 4.8). All saccharification studies were carried out in duplicates at least. The flasks were incubated in an orbital shaker at 150 rpm at 50 °C for 72 h. Samples from the reaction mixture were taken in time intervals (0, 6, 24, 48, and 72 h) and the enzyme activity was stopped by boiling samples for 10 min. Glucose content in the enzymatic hydrolysates was determined using high-performance liquid chromatography (HPLC). The enzyme activity of Celluclast 1.5 L® and Novozym 188 was determined as filter paper units (FPU).[34] One unit of FPU is defined as the amount of enzyme required to liberate 1 µmol of glucose from Whatman No. 1 filter paper per min at 50 °C. One cellobiose unit (CBU) is the amount of enzyme that converts 1 mmol of cellobiose to 2 mmol of glucose per minute.
Augmented ethanol production from alkali-assisted hydrothermal pretreated cassava peel waste
Published in Energy Sources, Part A: Recovery, Utilization, and Environmental Effects, 2021
Narendra Kumar Papathoti, Kansinee Laemchiab, Vineela Sai Megavath, Praveen Kumar Keshav, Parichat Numparditsub, Toan Le Thanh, Natthiya Buensanteai
After alkali-assisted hydrothermal pretreatment step, SSF of cassava hydrolyzate was performed in 500 mL Erlenmeyer flask, containing 150 mL fermentation media. The composition of fermentation media was followed as previously described by García-Aparicio et al. (2011). The slurried cassava hydrolyzate with supplements was autoclaved at 110°C for 10 min. After cooling the media to room temperature, SSF was initiated by aseptically adding 10% (v/v) K. marxianus inoculum, followed by addition of enzymatic solution containing cellulase (10 FPU/g substrate), α-amylase and glucoamylase (each containing, 450 IU/g substrate). The SSF was performed at 100 rpm, 40°C for 72 h time period. Samples from fermentation media were collected at regular time intervals and estimated for residual sugars ethanol concentration.