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SoC and NoC Design Methodology and Tools
Published in Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, Design of Cost-Efficient Interconnect Processing Units, 2020
Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi
An implementation of an adaptation layer includes software and hardware components, as shown in the left part of Figure 5.1. A typical software adaptation layer includes several sub-layers. The lowest sub-layer is usually represented by the board support package (BSP) and built in tests (BIT). The BSP allows all other software, including the Operating System (OS), to be loaded into memory and start executing, while BIT detects and reports hardware errors. On top of this sub-layer we have the OS and device drivers. The OS is responsible for overall software management, involving key algorithms, such as job scheduling, multitasking, memory sharing, I/O interrupt handling, and error and status reporting. Device drivers manage communication with external devices, thus supporting the application software. Finally, the software architecture sub-layer provides execution control, data or message management, error handling, and various support services to the application software.
Real-Time Operating Systems
Published in Leanna Rierson, Developing Safety-Critical Software, 2017
The BSP isolates the RTOS from the target computer processing hardware. It allows the RTOS kernel to be portable to various hardware architectures within the same central processing unit (CPU) family. “The BSP initializes the processor, devices, and memory; performs various memory checks; and so on. Once initialization is complete, the BSP can still function to perform low-level cache manipulations” [9], as well as some other hardware access (e.g., flash manipulation or timer access). Much of the BSP code operates in privileged mode and works closely with the RTOS. The BSP is sometimes called a hardware abstraction layer, a hardware interface system, or platform enabling software. It is customized for the specific hardware and is often implemented using C and assembly. The BSP is sometimes developed by the RTOS users (e.g., the avionics developer) using a template from the RTOS supplier—especially when the avionics utilize custom hardware. At other times, the BSP is provided and/or tailored by the RTOS supplier. Depending on the nature of the hardware, the BSP can be a rather large component.
Parallel Computing Models
Published in Vivek Kale, Parallel Computing Architectures and APIs, 2019
The BSP model has been proposed as a bridging model between hardware architecture and software development: the idea is to provide a standard on which both hardware architects and software developers can agree. Thus, software development can be decoupled from the details of a specific architecture, and software does not have to be adapted when porting it to a new parallel machine.
Programming models and systems for Big Data analysis
Published in International Journal of Parallel, Emergent and Distributed Systems, 2019
Loris Belcastro, Fabrizio Marozzo, Domenico Talia
Bulk Synchronous Parallel (BSP) [19] is a parallel computation model in which computation is divided into a sequence of supersteps (see Figure 6). In each superstep the following operations can be performed: Concurrent computation: each processor performs computation using local data asynchronously;Global communication: the processes exchange data among them according to requests made during the local computation;Barrier synchronisation: when a process reaches the barrier, it expects all other processes have reached the same barrier.The communication and synchronisation are completely decoupled, so as to guarantee that all the processes in a superstep are mutually independent. Moreover, this solution avoids problems due to synchronous message passing among processes (e.g. deadlocks). These features make the BSP programming model a very robust solution for developing scalable parallel applications.