China
Africa
Explore chapters and articles related to this topic
Low-Power Very Fast Dynamic Logic Circuits
Published in Christian Piguet, Low-Power CMOS Circuits, 2018
Because all clocked devices are connected to power and ground rails, they can be sized without excessive loading to improve speed, though care must be taken for the charge sharing between nodes A and B and between nodes C and D. In another example, a nonclassic flip-flop can be built from a split-output SP stage and an n-type split-output latch (or an SN stage and a p-type split-output latch), reducing the number of total transistors to eight and the number of clocked devices to two, which is shown in Figure 8.4(c). For a high clock, the SP stage is half-transparent, but the split outputs respectively to the p- and n-transistors in the following latch stage can never make them transparent, although the latch is in its nonlatching phase. Another method using flow tables and signal transition graphs (STG) has been presented in Piguet [6] and Piguet and Zahnd [7] to design similar circuits including dynamic flip-flops, aiming at race-free (or, today, speed-independent [SI]) circuits.
Asynchronous Circuits
Published in Wei Song, Guangda Zhang, Asynchronous On-Chip Networks and Fault-Tolerant Techniques, 2022
One advantage of adopting SI circuits is that they can be synthesized from behavioral circuit models described in signal transition graphs (STGs) [52, 57]. This allows complicated controllers to be designed with the help of circuit synthesis software. In certain scenarios, designers might choose to deliberately weaken the difference between QDI and SI circuits by considering all wires as isochronic forks, especially for the asynchronous controllers automatically synthesized by software. In this sense, SI circuits are also QDI.
Asynchronous Wrapper-Based Low-Power GALS Structural QDMA
Published in IETE Journal of Research, 2022
B.K. Vinay, S. Pushpa Mala, S. Deekshitha
Various design methodologies for GALS architecture include plausible clocks, asynchronous and locally synchronous modules. Plausible clocks avoid metastability by delaying the sampling of the clock until the arrival of data. In asynchronous interface design styles, the signal received from the outer clock domain is transferred to the local clock domain by synchronizers [8]. LS design styles analyze time bounds, overcoming the need for handshaking for data transfer [9]. Signal Transition Graphs (STG) represent the flow of positive and negative edges of the signals. In the proposed wrapper, a modified STG is adopted to reduce the communication time between two LS modules. A latch is added between two LS modules to store data for efficient communication [10]. Furthermore, a gated clock-based interface for GALS has been suggested wherein the external clock is gated to drive the local clock of the LS modules based on the request from port controllers [11]. The GALS interface uses First in First out (FIFO) buffers operating in asynchronous mode for data transfer between mixed clock-based LS modules [12]. The latency involved in synchronization between two LS modules is reduced using high bandwidth communication called STARI-based GALS interface deploying single-stage FIFO at receiver with the advantage of the stability of the clock [13]. Oliveira et al. [7] proposed a single-port controller for managing data communication in multipoint and point-to-point GALS for reduced area consumption. Stretchable clocks are realized to control the clock generator [14]. Asynchronous elements, such as join and fork, could be used, like “join” various data signals and send to GALS module and “fork” being used to send data to various sinks [3].