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Heterogeneous Memory Design
Published in Tomasz Wojcicki, Krzysztof Iniewski, VLSI: Circuits for Emerging Applications, 2017
Chengen Yang, Zihan Xu, Chaitali Chakrabarti, Yu Cao
Different memory combinations have been studied for the main memory level. Most of the work has been geared toward partially replacing DRAM, which has problems of large power consumption, especially due to refresh power and is not amenable to aggressive scaling. Unfortunately, PRAM has high programming energy and reliability problems. Thus, most approaches try to hide the write latency of PRAM and reduce the number of PRAM accesses by putting DRAM/Flash buffer or cache before PRAM-based main memory. The major differences among these architectures are memory organization, such as buffer/cache size or line size, and data control mechanisms.
Parallel Computing Models
Published in Vivek Kale, Parallel Computing Architectures and APIs, 2019
A parallel random-access machine (PRAM) consists of a bounded set of identical processors {P1,…, Pn}, which are controlled by a global clock. Each processor is a RAM that can access the common memory to read and write data, and a local memory to store private data. Each processor can access any location in the common memory in unit time, which is the same time needed for an arithmetic operation.
Low-temperature growth of γ phase in thermally deposited In2Se3 thin films
Published in Phase Transitions, 2018
Rozalin Panda, R. Naik, N. C. Mishra
In2Se3 (IS) is a group III2–VI3 direct bandgap semiconducting compound which have potential applications in photovoltaic cells [1], optoelectronic devices [2], solid solution electrodes [3], electro and photo memory devices [4], diodes [5], photoelectrochemical application [6], Phase change random access memory (PRAM) [7] and it is also used as a buffer layer for CIS solar cells [8]. The in2se3 thin film is used as a window layer [3] in CIS/In2Se3 solar cell in the γ phase due to its wider band gap of 1.8 eV [9]. Also, In2Se3 is used as an absorber layer [10] in CdS/In2Se3 solar cells in β form due to its band gap of 1.55 eV [11]. Whether window or absorber layer applications, it is desired to use indium selenide in thin film form as a single phase material. It is, however, difficult to produce single phase and stoichiometric indium selenide due to the complex phase diagram of In/Se based systems permitting the simultaneous emergence of phases such as InSe, In2Se3, In4Se3 and In6Se7 [12]. In addition to the complexity arising due to this compositional variance, In2Se3 itself, depending on the preparation conditions, evolves into five different forms such as α, β, γ, δ and κ [13,14] exhibiting different structural, optical and other properties [15]. A large number of studies were carried out on this material [11-21], but the results were rather confusing because of the existence of numerous phases in the as-prepared sample. During the film growth process, there are competitions for preferential occupation among different phases of indium selenide due to which amorphous phases of indium selenide forms along with crystalline phase [22].
Biological function simulation in neuromorphic devices: from synapse and neuron to behavior
Published in Science and Technology of Advanced Materials, 2023
Hui Chen, Huilin Li, Ting Ma, Shuangshuang Han, Qiuping Zhao
Some models can be proposed to explain how a neuron works, such as Hodgkin-Huxley (HH) model [86,87], McCulloch-Pitts (MP) model [88,89], oscillation model [90,91] and integrate and fire (I&F) model [92,93]. Among them, I&F concentrates on whether a neuron should fire a spike as action potential to be transmitted to the next neuron or not by comparing the local graded potential (LGP) with the threshold. Two forms of I&F have presented in neuron: integrate-and-fire (IF) and leaky integrate-and-fire (LIF). Therein, IF neuron will retain LGP boosting forever until it fires even when it receives a subthreshold signal, whereas LIF neuron leaks out LGP in a short time when it is lower than the threshold [94]. I&F model can be well described in Figure 6(a). Simply, the input current is integrated and the membrane potential is charged in the I&F neuron. Once the membrane potential reaches the threshold voltage (Vth), the neuron will generate spikes to the next neuron and reset the membrane potential. Usually, the threshold switching (TS) devices, including resistive random access memory (RRAM) [96], flash memory [97], phase change random access memory (PRAM) [98], ferroelectric thin-film transistors and electrolyte film transistors [11], are used to mimic the I&F neuron, and also have to be combined with other types of devices such as capacitor and resistor, in which a circuit can be well employed to implement this function (Figure 6(b)). In this, the capacitor is as the membrane capacitor (Cm) to integrate the input current, and the resistor represents an output resistor (Rout) to generate output spikes by voltage division with the TS device. The input electrical pulses and their interval charge and discharged the capacitor (Figure 6(c)), respectively. When the TS device is initially in the off-state, charging effect is over discharging one due to the slow discharge. In this case, the total charges increase as the pulse is applied. Next, once the increased charges make the voltage drop of the TS device (VTS) reach Vth, the neuron circuit starts the fire process and generates the output spikes (Vout) because the TS device switches from the off-state to the on-state. At the same time, the capacitor is discharged quickly so that VTS decreases and the TS device returns to the off-state (reset). Then, this neuron circuit returns to the integration process [95].