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Digital Circuit Design with Very-High-Speed Integrated Circuit Hardware Description Language
Published in A. Arockia Bazil Raj, FPGA-Based Embedded System Developer's Guide, 2018
We used the vertical bar (|), which is equivalent to the or operator, to illustrate how to express a range of values. This is a useful operator to indicate ranges that are not adjacent, for example, 0 to 4 | 6 to 10. It should be noted that the combinational circuits can also be expressed in other ways, using concurrent statements such as the with–select construct. Since the case statement is a sequential statement, one can have nested casestatements as well. A loop statement is used to repeatedly execute a sequence of sequential statements. The syntax for a loop is: [ loop_label :]iteration_scheme loop sequential statements [next [label] [when condition]; [exit [label] [when condition]; end loop [loop_label];
Programming in MATLAB
Published in José Miguel, David Báez-López, David Alfredo Báez Villegas, ® Handbook with Applications to Mathematics, Science, Engineering, and Finance, 2019
José Miguel, David Báez-López, David Alfredo Báez Villegas
The while loop is used to repeat a set of instructions for an unknown number of times. The difference between a while loop and a for loop is that the for loop has to be repeated a known number of times. The format for the while loop is: while condition statement_1 … statement_n end
Solidity Essentials
Published in Sandeep Kumar Panda, Ahmed A. Elngar, Valentina Emilia Balas, Mohammed Kayed, Bitcoin and Blockchain, 2020
Loops are used where the repetition of some codes is required; it is programmed using for, while, or do while. For example, while (condition){/ * These statements within these curly braces will executerepeatedly until the condition fails */}
Study and evaluation of FPGA reconfiguration during service operation for environment-adaptive software
Published in International Journal of Parallel, Emergent and Distributed Systems, 2023
The FPGA offload pattern search time can be shortened by preparing multiple FPGA servers and performing measurements in parallel. In addition, although the offload candidate loop statements are narrowed down on the basis of the arithmetic intensity and resource usage, it is also effective to reduce the number of narrowed-down measurements by the number of loops. The FPGA offload can be further speeded up by changing the logic to consider the algorithm of the entire function, rather than simply offloading the loop statement. For example, tdFIR loop statement offload improves performance by several times with Intel FPGA, but when the entire tdFIR function is offloaded to logic with OpenCL implemented with optimized algorithms, Intel Arria 10 FPGA improves performance by 21 times. Therefore, we will consider using such a function block offload together with the loop statement.
Study and evaluation of automatic offloading method in mixed offloading destination environment
Published in Cogent Engineering, 2022
First, for preparation, we proposed an automatic offload method for loop statements for a multi-core CPU as one of various offloading destination environments, with reference to the evolutionary computation method for a GPU. Next, we studied the order of offload trials for each offloading device and the speed-up method when there were multiple offload candidates with one node. Specifically, the function block offload for multi-core CPU, the function block offload for GPU, the function block offload for FPGA, the loop statement offload for multi-core CPU, the loop statement offload for GPU, and the loop statement offload for FPGA are verified in this order. This is because function block offloading can be faster than loop statement offloading, and FPGA verifications take longer time to measure performance. Next, as a result of six offload verifications, if there are multiple offload candidates that can be accelerated, the implementation checks whether these candidates are at the same node. When different processes can be offloaded to different devices at the same node, these processes are offloaded to the devices, and the performance is measured. If the performance is higher than those for the other patterns, the offloading pattern is adopted. If it is not possible to offload to the same node, the fastest pattern is adopted among the six offload verifications of each device.
Study and evaluation of automatic GPU offloading method from various language applications
Published in International Journal of Parallel, Emergent and Distributed Systems, 2022
As for the objects to be offloaded, we focus on the loop statement and function block of the program. Loop statements are the first target for offloading because most processing of programs that take a long time is spent in loops. On the other hand, with regard to function blocks, when speeding up specific processing, an algorithm suitable for the processing content and processing hardware is often used, so there is a case where processing can be greatly speeded up compared with offloading individual loop statements [24]. The performance of programs is improved by replacing frequently used function blocks such as matrix calculation and Fourier transform with CUDA libraries implemented with algorithms suitable to GPU.