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A Review on SEU Mitigation Techniques for FPGA Configuration Memory
Published in IETE Technical Review, 2018
T. S. Nidhin, Anindya Bhattacharyya, R. P. Behera, T. Jayanthi
A k-input look-up-table (LUT) can implement any function with k inputs; it acts as a function generator. Figure 6 illustrates the logic resources structure. The configuration bits are stored in the SRAM cells. A logic error can lead to flip one of the entries of the LUTs, which alter the functionality of the mapped logical function.