China
Africa
Explore chapters and articles related to this topic
Logic Design Fundamentals
Published in Joseph Cavanagh, Computer Arithmetic and Verilog HDL Fundamentals, 2017
Outputs from a synchronous sequential machine can be asserted at a variety of different times depending on the machine specifications. In some cases, the output assertion and deassertion may not be specified, giving substantial flexibility in the design of the λ output logic. A contributing factor in considering the output design is the possibility of glitches. Glitches are spurious electronic signals caused by varying gate delays or improper design techniques, in which the design was not examined in sufficient detail using “worst case ” circuit conditions. Glitches are more predominant in Moore machines where the outputs are a function of the state alphabet only.
Data Converter
Published in Arjuna Marzuki, CMOS Analog and Mixed-Signal Circuit Design, 2020
Among the factors that contribute to the glitch phenomenon are matching errors in switches and driver circuits, or time skew between switching signals, voltage-dependent complementary metal-oxide semiconductor (CMOS) switches, etc. For a short period of time, a false code could appear at the output. For example, for 3-bits binary code DAC, when the digital input changes from 011 to 100, if the MSB switch is turned on earlier than the other switches, the intermediate state 111 will appear during the process of the transformation of the switch signals and at the output terminal a glitch will appear [2].
Analysis of Temperature-Dependent Crosstalk for Graphene Nanoribbon and Copper Interconnects
Published in IETE Journal of Research, 2022
Sandip Bhattacharya, Debaprasad Das, Hafizur Rahaman
The crosstalk noise analysis have been performed for coupled interconnect system for both Cu and GNR interconnects with three different chip-operating temperatures same as crosstalk delay analysis for various interconnect length (10 µm ≤ l ≤ 100 µm). In Figure 3, step-5 to step-8 depicts the effect of crosstalk noise. In our analysis, we have performed crosstalk noise measurement. Under this noise measurement, we have computed the noise peak, noise area, and noise width, shown in Table 1. The overshoot/undershoot peak, area, and width also computed, shown in Table 2. In our analysis, we have focused on noise analysis rather than overshoot/undershoot analysis because results are almost same with noise analysis. The basic difference between the noise and overshoot/undershoot analysis is that for noise peak (rise/fall glitch) calculation the noise level starts from 0 V, but in case of overshoot/undershoot peak calculation noise level starts from supply voltage, i.e. ±0.7 V. The crosstalk noise can be measured at two different nodes known as near-end and far-end of the coupled circuit shown in Figure 2(b).
A Novel Classification and Synchronous Noise Removal During Fetal Heart Rate Monitoring
Published in IETE Journal of Research, 2021
The FIR filters such as low pass, multiband, unsigned coefficient, adaptive band stop, and adaptive multiband are simulated under Xilinx ISE 9.1i and Cadence Virtuoso of 90 nm technology for obtaining precision and accuracy in measured parameters. It is commonly observed from Table 3 that the area has drastically reduced from an array multiplier to that of an HPM-based Booth multiplier. But a key point to be noted is that the number of glitches and hence the power is also increasing as the input bit rate is gradually increased. In order to circumvent the increase in glitch rate and henceforth the power, a glitch-free HPM-based multiplier stage was proposed and simulated, and it was found that the adaptive multiband filter outweighed all other filters in terms of almost all of the performance metrics such as area, power, delay, and efficiency. The power dissipation can be easily calculated using the formula Ptotal = pt(CLVVddfclk) + IscVdd + IleakageVdd [24]where the equation depends on transition rate, voltage swing, which will nominally be considered as glitch, supply voltage, frequency, leakage current, and short circuit current.
Deploying a Recall Mitigation Framework for Systems Engineering
Published in Engineering Management Journal, 2018
Md Shahnoor Amin, Timothy Blackburn, Andreas Garstenauer
Part of the FMEA involved developing boundary diagrams for major components and subsystems that could cause recalls due to inadvertent operation. Exhibit 10 is one example of a boundary diagram, showing how the complex electromechanical wiper system works in cars. The EPM developed a system boundary diagram of the wiper system, and determined the system interactions that could cause a recall. The wiper system was a good example of a commonly-used feature that relies on both hardware (e.g. electric wiper motor) and software for operation. There are multiple input signals into the system, which then impact the output motor speed. For instance, if there was a glitch in the windshield wiper software that caused the motor’s duty cycle to be beyond its rated capacity, it could overheat, cause a fire hazard, and be subject to a serious safety recall (NHTSA, 2011). Defects to the wiper system or any other safety-critical component are required be fixed by the OEM to prevent human injury according to the Magnusson-Moss Warranty Act (FTC, 2015). Any open recalls must be communicated by the EPM to the warranty team and eventually cascaded to potential owners (Johnson, 2016). Both FTA and FMEA were used to identify the three variables in this study: fuel economy, warranty duration, and crashworthiness.