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Effects of Terrestrial Radiation on Integrated Circuits
Published in Robert Doering, Yoshio Nishi, Handbook of Semiconductor Manufacturing Technology, 2017
By far the most effective method of dealing with soft errors in memory components is by employing additional circuitry for error detection and/or correction. In its simplest form, error detection consists of adding a single bit to store the parity (odd or even) of each data word (regardless of word-length). Whenever data is retrieved, a check is run comparing the parity of the stored data to its parity bit. If a single error has occurred, the check will reveal that the parity of the data does not match the parity bit. Thus the parity system allows for the detection of a soft error for a minimal cost in terms of circuit complexity and memory width (only a single bit is added to each word) as illustrated in Figure 31.14a. The two disadvantages of this system is that the detected error cannot be corrected, and if a double error has occurred, then the check will not reveal that anything is wrong, since the parity will match. This is true for any even number of errors. For example, if the data was stored with odd parity, the first error changes the odd parity to even parity (detectable error), but the second error changes the parity back to odd (non-detectable error).
Effective Brain Computer Interface Based on the Adaptive-Rate Processing and Classification of Motor Imagery Tasks
Published in Mridu Sahu, G. R. Sinha, Brain and Behavior Computing, 2021
Saeed Mian Qaisar, Reem Ramadan, Humaira Nisar
The grace of the adaptive rate acquisition, a notable compression gain of 13.67-fold, is attained by the proposed solution. The computational complexity is also reduced at every stage of the system by using adaptive rate processing techniques instead of time-invariant techniques. The average gain for both intended subjects is calculated. The benefit in terms of additions and multiplications for the ARFIR is 30.57 and 32.12 folds, respectively. Reduction of circuit complexity is accomplished by using a 5-bit resolution EDADC as opposed to a 16-bit resolution done in previous studies. As a result of both, power efficiency of the system is inherently improved.
Design and Analysis of a Hybrid 4-2 Approximate Compressor for Multiplication
Published in T. Kishore Kumar, Ravi Kumar Jatoth, V. V. Mani, Electronics and Communications Engineering, 2019
K. Satisha, M. V. Ganeswara Rao
In this chapter, we are using an approximate (inexact) compressor. By using design 1 and design 2, four 8 × 8 bit approximate or inexact multipliers are designed to reduce the circuit complexity and to increase the performance. Design 3 multiplier was implemented as a proposed method. ModelSim is used to generate the simulation results. Inexact or approximate computing is a prominent model for computation at nanometer technology. A significant operational advantage is offered by computer arithmetic for inexact computing; an extensive literature exists on inexact or approximate adders.
Dual Output and Dual-Frequency Resonant Inverter-based Induction Heating Using ADC Control
Published in IETE Journal of Research, 2023
Kumaraswamy A, Ananyo Bhattacharya, Pradip Kumar Sadhu
A DODF resonant converter with reduced cost and improved efficiency is proposed in this paper. The proposed topology eliminates the need for rectifier and extra AC link capacitors which reduces the circuit complexity and can be employed for modern induction heating. All MOSFETs in this direct AC-AC converter are operated at ZVS operation and hence reduce the switching losses. The proposed topology is capable of achieving independent power control, higher conversion efficiency, and dual load operation at any time instant, which cannot be achieved by the existing AC-AC converters. Further, the proposed scheme can be readily extended to an all-metal induction heating system application. The performance of the proposed system is validated by simulation results. The proposed scheme has advantages like reduced components, less voltage stress, independent load control, less complexity, and high efficiency which makes it employable for all practical induction heating applications.
36 μW fourth order sigma-delta modulator using single operational amplifier
Published in International Journal of Electronics Letters, 2021
Vivek Sharma, Nithin Kumar Y.B., Vasantha M.H.
In Figure 1 the power and Figure Of Merit Walden (FOMW) against the different bandwidth of sigma-delta modulator are shown (Murmann, 1997–2018). The power consumption of ΣΔM increases for increasing bandwidth and for signal range, i.e. greater than 10 kHz, the reported consumption is mostly confined to 100 µW. However, Op-Amp sharing and MASH architecture using multi-bit DACs have mismatch errors and the need of DEM techniques adds to circuit complexity. Further, the timing issues due to multi-bit DACs causing noise leakage and the rise in power consumption requires attention. The objective of the proposed design is to provide the design solution around 10 kHz bandwidth having power dissipation in the range of 10 µW to 100 µW with appreciable FOMW (i.e. less than 0.5 pJ/conversion) so as to fit in the state of art related to FOMW.
Design and analysis of coupled-inductor Cockcroft–Walton-switched-capacitor boost DC–AC inverter
Published in International Journal of Electronics, 2023
A novel closed-loop structure of the CICWSC inverter is presented to achieve the target of boost DC–AC conversion/regulation, and the related derivations of analysis/design are included in this study as well. The power part is capable of reaching a wide range of DC–AC gain: (, ). The control part is primarily realized by this chip of D35-104B-E0013, implemented via TSMC full-custom fabrication (TSMC 0.35 μm 2P4M, 750 × 700μm2, 3.3 V, 3.889 mW, max 100 kHz), and is designed not only for the timing control applied to different topologies but also for the enhancement of output regulation and/or robustness. The simulations via using OrCAD are illustrated to examine the analysis/design validity, and the experiments via testing on the prototype are presented to confirm the efficacy. Here, this study has gained a few merits to summarize below. (i) As Section 5 shows (e.g., from DC into AC ,), this CICWSC prototype practically attains the DC–DC gain of 12 times (DC–AC gain of 6 times) merely by employing four capacitors, one coupled inductor, and one switch (three switches). (ii) This proposed CICWSC is in essence a kind of SC power converter (excluding one coupled-inductor device). Thus, it will be a hopeful future for a SC-based power system on chip. (iii) For increasing the total step-up gain, it is practicable to change , of the coupled inductor and/or to extend the stage number of CWSC doubler in this scheme. Table 1 demonstrates a quantitative comparison between CICWSC and some others. In view of lifting the gain up more effectively, it is found (as operating at the same ) that this CICWSC has an excellent gain performance relatively with fewer devices. In other words, it is flexible enough to allow room for compromise between the device count, turn ratio, and ratio cycle. For example, if some high gain is asked, extending the stage number of the CWSC doubler will be helpful to reduce the turn ratio of the coupled inductor so as to lower the volume/weight of the magnetic device (even or improve magnetic bias/saturation). (iv) Because all roots are demonstrably situated in LHP, the CICWSC inverter is with an inherent performance of local stability. Thus, it can help allow us to adopt a simpler controller (e.g., P-type) and reduce the circuit complexity of control part.