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Low-Power Cache Design
Published in Christian Piguet, Low-Power Processors and Systems on Chips, 2018
Vasily G. Moshnyaga, Koji Inoue
Besides zeros, just a few distinct values occupy the majority of cache locations [55]. These values are scattered somewhat uniformly across cache and remain almost the same during program run. We can exploit this phenomenon by dividing the data array into two parts, as depicted in Figure 8.12 [55]. The frequent values are stored in encoded form (2 to 7 bits) in the low-bit data array, while nonfrequent values are stored in unencoded form (32 bits) in both data arrays. A flag bit is attached to each word in the low-bit data array to indicate whether the word is encoded or not. On read access, the cache reads out the low-bit data array; if the flag points to an encoded word, then it decodes the word and completes the access without activating the high-bit array. Otherwise, it does not perform decoding but takes another clock cycle to read the remainder of the word from the second data array. The full value in this case is obtained by concatenating the two parts of the word. On write access, the incoming value is checked within the CAM-based encoder; if it is frequent, it is stored in cache in the encoded form jointly with the flag. Otherwise, the flag is stored with unencoded, original word. Although up to 32% energy saving has been reported for the eight-way 64-KB cache, the main challenge exists in implementation of the CAM-based data coding-decoding (codec) capable of detecting frequent values with low impact on performance and area.
Acquiring and Processing Turbulent Flow Data
Published in Richard J. Goldstein, Fluid Mechanics Measurements, 2017
In digital processing the first step is to convert the anemometer output into digital form compatible with the computer and interface bus. Digital processing systems generally have 8-, 12-, 16-, or 32-bit character lengths. Computers generally use 16- and 32-bit words (“word” reflects the natural width of the computer’s CPU registers). In computer jargon, a 4-bit array is a “nibble” and an 8-bit array is a “byte.” A bit is a binary integer, and a binary word is a sequence of bits representing a number. For instance, 101 is a 3-bit word representing the decimal number 5. The right-hand bit, which is called the least significant bit, is the units column, the next bit is the 21 column, and the next bit, the most significant bit in this case, is the 22 column. An 8-bit array can represent any decimal integer between 0 and 256; a 12-bit array, 0-4095; a 16-bit array, 0-65535; etc. An 8-bit array allows maximum resolution of 1 part in 256 (1/2%); a 12-bit, 0.025%; a 16-bit, 0.0015%; etc. Eight-bit resolution may require offsetting an unlinearized hot-wire signal before digitizing, whereas 12-bit resolution would allow digitizing the signal directly.
Design and implementation of conflict detection algorithm VHTB
Published in Amir Hussain, Mirjana Ivanovic, Electronics, Communications and Networks IV, 2015
Ying Liu, Fuxiang Gao, Ying Xie
The conflict detection algorithm based on signature refers to Bloom Filter. The read/write set would be mapped to a bit-array. Its length is m. This mapping needs k hash functions. And the bit-array is called a signature (Sanchez 2007). So we can use a finite signature to express an infinite set. It can save a lot of memory space and improve the searching efficiency. Signature has the same advantage as Bloom Filter. It is effective but has some false positives (Zilles 2007). When a false positive happens, one of the concurrent transactions must be aborted. But there is no conflict actually. The false positive rate is an important parameter for system performance. Many conflict detection algorithms based on signature were proposed, such as True Bloom, Hash Bloom and Vertical Hash Bloom. To make good use of the signature, we have studied the advantages of VHB and True Bloom.
Faster quantum concentration via Grover's search
Published in International Journal of Parallel, Emergent and Distributed Systems, 2023
Algorithm 2 extends the main idea of Algorithm 1 to routing active inputs in a bounded capacity fat-and-slim concentrator.2 As in Algorithm 1, the inputs are divided into fat and slim sections, but this time, the slim section is placed on the left and the pseudo-fat section is placed on the right in Figure 2. An m-bit array, named out is added to mark the outputs. The first for loop pairs the active inputs in the slim section with outputs whose indices coincide with those of the active inputs, while marking those outputs by entering ‘0's into out in their index positions. The second for loop finds the active inputs in the pseudo-fat section on the right. The last nested loop pairs the active inputs in the pseudo-fat section on the right by searching for an available output from among the set of outputs to which each active is connected by a crosspoint.
Determination of Effective Signal Processing Stages for Brain Computer Interface on BCI Competition IV Data Set 2b: A Review Study
Published in IETE Journal of Research, 2023
Malan et al. [9] used Genetic Algorithm (GA), PCA, Relief-F, Neighbourhood Component Analysis (NCA), and RNCA methods and compared the methods with each other according to classification performance and number of features. The GA, PCA, Relief-F, and NCA, which are more conventional methods, showed higher kappa values than the other methods by using less numbers of features. GA solves the feature selection problem by considering a data structure where a chromosome population is selected. Each chromosome is coded as a binary bit array [58]. The length of the array is taken as equal to the dimension of the features. Thus, each bit in the array represents a specific feature. The features having a high bit value are selected for classification, while the features having low bit value are rejected. After that, the fitness value of each chromosome in the population is calculated for kappa value and/or classification accuracy by using a learning algorithm.
A 2.71 fJ/conversion-step 10-bit 50 MSPS split-capacitor array SAR ADC for FOG systems
Published in International Journal of Electronics, 2022
Chua-Chin Wang, Ralph Gerard B. Sangalang, Meng-Jie Wu, Tzung-Je Lee, Yi-Jen Chiu, Lean Karlo S. Tolentino, Oliver Lexter July A. Jose
The proposed 10-bit 50 MS/s SAR ADC architecture is shown in Figure 4. The proposed design is fully differential to minimise the noise effects coming from the substrate and the supply. It is composed of two capacitor arrays, namely, the most significant bit array (MSB Array) and the least significant bit array (LSB Array), serving as the digital-to-analog converters used for coarse and fine conversion, respectively. Two unity gain buffers are introduced to separate the coarse and fine conversion arrays replacing the bridge capacitor in those traditional split-capacitor arrays. By this, the total capacitance are realised with smaller sizes compared to traditional counterparts. The size reduction is from to times the size of a unit capacitor generalised for N-bit resolution theoretically. For instance, the capacitor array exhibits 90.63% size reduction for the 10-bit resolution. All the circuit details will be disclosed in the following text.