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Lighting and Communications: Devices and Systems
Published in Zabih Ghassemlooy, Luis Nero Alves, Stanislav Zvánovec, Mohammad-Ali Khalighi, Visible Light Communications, 2017
Luis Nero Alves, Luis Rodrigues, José Luis Cura
One major benefit for using VLC is the ability to provide simultaneous illumination and data communications using the same lighting device. However, light sources with high (fast) switching features as required for data communications are not always suitable for illumination purposes, since the lighting characteristics would be highly dependent on the communication signal. In order to improve LED lighting and modulation characteristics, it is necessary to combine the communication signal with LED biasing required to support lighting features. This can be achieved using one of two approaches. The simplest one is to rely on a bias tee. The other relies on dedicated circuits able to separate and provide independent control of both functions. The bias tee consists of a passive device with three ports one for signal input, other for biasing, and another providing the combined biasing and signaling functions. The basic operation relies on frequency selective networks. For signaling purposes, the bias tee should provide broadband coverage and provide strong attenuation at low frequencies. For biasing purposes, the bias tee provides strong attenuation for signal frequencies and pass the low frequencies. Achieving good performance relies on the matching quality of the output port. This requires that the load impedance must be matched to the bias tee, otherwise frequency selectivity becomes load dependent. Concerning the LED driving case, the load impedance is the LED, presenting an impedance dependent on the biasing current. There are several design possibilities for bias tee able to maintain performance even with impedance variations. Simple possibilities such as the one in Figure 2.30a, do not support load impedance independence. In this simple case a capacitor is used to feed the signal component and one inductance for the biasing.
System-on-Chip Substrate Crosstalk Measurement Techniques
Published in Thomas Noulis, Noise Coupling in System-on-Chip, 2018
Konstantinos Moustakas, Thomas Noulis, Stylianos Siskos
The NMOS transistor is connected to the spectrum analyzer 50 Ω input trough a bias tee. A bias tee is used to set the DC bias point independently of the AC signal. The high impedance of the inductor does not allow the AC signal to flow through it, but there is a short-circuit at DC that sets the bias point of the drain at 0V. The capacitor is an open circuit at DC and a short circuit at AC, providing a low impedance path from the AC signal to the spectrum analyzer input. Since the input is connected to ground, typically the NMOS has to be biased from negative power supplies [15]. This is easy in simple test chips, but is impractical is production environments. The drain potential is set to 0V to achieve the maximum VDS, so the gain is not decreased by CLM. The gain depends on the bias current and the transistor size, as seen by Equation 10.12. gmb≅0.1–0.3gm,gm=2μnCoxWLID where gm is the gate-to-source transconductance, gmb the body-to-source transconductance, μn the electron mobility, Cox the gate oxide capacitance, ID the drain current, W the width, and L the length of the transistor. The values of the gate-source and body-source transconductance calculated via simulation are: gm = 100 mS, gmb = 16.1 mS, therefore gmb/gm = 0.161. Because the measurements are high-frequency, S-parameter analysis is used to characterize the sensor performance. The NMOS dimensions are given by Table 10.1 and the simulation results by Table 10.2. In Figure 10.7, the S21 parameter characterizing the frequency response and the gain of the sensor is illustrated for process and temperature variations. In Figure 10.8, the intrinsic noise voltage in the output due to the sensor is also depicted.
Reconfigurable Corner Truncated Square Microstrip Patch Antennas for Wireless Communication Applications
Published in IETE Journal of Research, 2020
Anantha Bharathi, Lakshminarayana Merugu, P. V. D. Somasekhar Rao
Figure 17 shows the polarization and frequency reconfigurable antenna, designed using uniplanar FR4 Epoxy substrate with r = 4.4 and a thickness of 1.6 mm. It consists of a rectangular ground plane of dimensions Lg× Wg with a square ring slot etched at the centre. Inner square patch formed by the square ring slot is perturbed such that five conductors are formed. Four parasitic triangular conductors are connected to the centre rhombic conductor using four PIN diodes D1 to D4. A 50 Ω CPW-to-Slotline transition is used to feed the square ring slot antenna. It feeds the antenna either in CPW mode or slot line mode, using the diodes D5 and D6. The DC bias circuit required for the switching of PIN diodes D1 to D4 is placed in the gap between centre rhombic conductor and parasitic triangular conductors. The bias circuit consists of a PIN diode in series with a capacitor of 33 pF to provide RF continuity. A conducting pad is located between PIN diode and capacitor to which an inductor of 47 nH is connected to isolate DC from RF. The other end of inductor is connected to the DC terminal. Four independent bias voltages are applied to the respective DC terminals V1 to V4 for biasing the PIN diodes D1 to D4. The DC ground required for PIN diodes D1 to D5 is achieved by grounding the centre rhombic conductor through an RF choke of 47 nH. The DC ground for D6 is achieved by directly grounding its cathode. The bias voltage for diodes D5 and D6 is provided along with RF signal using a bias tee. A bias tee is a three port device with two input ports and one output port. The RF and DC voltage (V5) are applied to two input ports and (RF + DC) is generated at output port.