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Division and Square Root
Published in Keshab K. Parhi, Takao Nishitani, Digital Signal Processing for Multimedia Systems, 2018
Hosahalli R. Srinivas, Keshab K. Parhi
Tables 20.2 and 20.3 list the cycle time and area required for a recursion stage of the radix 2 and radix 4 division algorithms that have been discussed. The major factor driving the need for higher radix schemes is to reduce the total computation time required to perform division. An immediate requirement for higher radix division schemes to satisfy this is to reduce the time per iteration step. Recently proposed higher radix division schemes strive to reduce this iteration time. An important effect in resorting to higher radix schemes is that the contribution of negative factors such as register loading and buffer delays are reduced. This is true because these delays now appear only in W/log2r iterations (for a radix r > 2) instead of W for radix 2. Using higher radix results in a wider range for the partial remainder causing the quotient selection logic to be a function of more number of digits. Furthermore, divisor multiple selection for a larger quotient digit set adds extra delay.
Number Systems and Codes
Published in Sajjan G. Shiva, Introduction to Logic Design, 2018
The radix divide and multiply algorithms are applicable to the conversion of numbers from any base to any other base. When a number is converted from base p to base q, the number in base p is divided (or multiplied) by q in base p arithmetic. Because of our familiarity with decimal arithmetic, these methods are convenient when p equals 10. In general, it is easier to convert a base p number to base q (p ≠ 10, q ≠ 10) by first converting the number to decimal from base p and then converting that decimal number to base q (i.e., (N)p → (?)10 → (?)q), as shown by the following example.
Number Bases, Codes, and Binary Arithmetic
Published in Eugene D. Fabricius, Modern Digital Design and Switching Theory, 2017
In a positional number system any number can be represented by a string of characters, with each character position assigned a weight which is a power of the radix or base. In the familiar decimal system the number 1234.5 represents 1 ¥ 1000 + 2 × 100 + 3 × 10 + 4 × 1 + 5 × 0.1. Except for leading and trailing 0s, the representation of any number in positional notation is unique. (i.e., 01234.500 is the same number as 1234.5). This idea will be pursued further when we come to complementing numbers, where the representation of the complemented number will depend upon how many leading and/or trailing 0s are to be complemented.
DPL-based novel CMOS 1-Trit Ternary Full-Adder
Published in International Journal of Electronics, 2021
Aloke Saha, Rakesh Kumar Singh, Pragya Gupta, Dipankar Pal
Ever-increasing demand for battery-powered sophisticated portable embedded electronic systems makes application-specific processing attractive as compared to its general-purpose counterpart. High-speed processing along with low power dissipation is the primary challenge to meet an aforesaid objective (Saha, Kumar et al., 2017; Saha, Pal et al., 2017; Saha et al., 2013, 2018). Rapid dimensional downscaling of solid-state devices leads to a significant increase in functional density on single monolithic Integrated Circuit (IC). Binary (Radix-2) is the best known and most favoured number system to represent digital data due to inherent ON/OFF characteristics of solid-state devices. High interconnect complexity however makes binary-based processing less attractive in VLSI/ULSI community because of increased fabrication complexity, pin-out difficulty, fan-in-fan-out driving issues, reduced reliability, hot-spot generation and so on (Saha & Pal, 2018). Extensive investigation on Multi-Valued Logic (MVL) revealed that ternary (Radix-3) logic can be a feasible alternative to binary processing in the digital world (Hurst, 1984; Saha & Pal, 2020; Wu, 1990). Higher information-carrying capability makes ternary digital data to process, store and communicate more efficiently than the binary digital data. Further, being more close to the natural base ‘e’ (‘e’ ≈ 2.718) the base-3 (ternary) system can offer reduced conversion error as compared to base-2 (binary) system (Saha & Pal, 2018). Additional details on ternary logic and its applicability to replace binary digital system can be found in (Ghiye et al., 2014; Hurst, 1984; Mounika et al., 2016; Saha & Pal, 2018, 2020; Srinivasu & Sridharan, 2017; Tabrizchi et al., 2017; Vudadha & Srinivas, 2018; Vudadha et al., 2018; Wu, 1990), which resulted in the renewed interest of circuit designers in ternary-digital-system.