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Design and Verification Languages
Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
The third layer of PSL, the verification layer, instructs a verification tool what tests to perform on a particular design. It amounts to a binding between properties defined with expressions from the Boolean and temporal layer, and modules in the design under test. The following simple example vunit ex1a(top_block.i1.i2) { A1: assert never (ena && enb); }
Design and Verification Languages
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC System Design, Verification, and Testing, 2018
The third layer of PSL, the verification layer, instructs a verification tool what tests to perform on a particular design. It amounts to a binding between properties defined with expressions from the Boolean and temporal layer, and modules in the design under test. The following simple example:
Investigation of distance relay settings under normal and stressed conditions in a wind farm environment
Published in International Journal of Ambient Energy, 2023
Priya R. Pattanaik, Basanta K. Panigrahi, Subhendu Pati, Smaran K. Sanyal
Microprocessor relay uses software-based numerical measuring techniques for control and monitoring tasks. These relays have the ability to communicate with other relays installed at different substations. IEC 61850 protocol and GOOSE (Generic Object Oriented Substation Event) messaging enable relays to exchange binary information regarding their zone status. Interfacing between relay outputs and switching devices or any other equipment is achieved through the relay outputs. The relay output status can be depending upon programmable schemes logic (PSL). The PSL includes multiple logic gates, multiple timers, the ability to invert signals and issue interrupts to a microprocessor. The inputs to the PSL are data available at the relay location. The communication interface in a distributed bus protection configuration ensures that all the remote relay units are connected through communication with a central master unit.
Industrial ontologies for interoperability in agile and resilient manufacturing
Published in International Journal of Production Research, 2022
Farhad Ameri, Dusan Sormaz, Foivos Psarommatis, Dimitris Kiritsis
The domains of process planning, production planning and scheduling have seen many research efforts devoted to knowledge-based approaches and integration of those functions. Early works were based on rule-based expert systems with symbolic product models, such as GARI (Descotte and Latombe 1984) RTCAPP (Park and Khoshnevis 1993) and others. This was followed with a phase where a direct link to a feature-based CAD model was used as input (XCUT (Hummel and Brooks 1988), 3IPP (Khoshnevis, Sormaz, and Park 1999)). IMPlanner system (Sormaz*, Arumugam, and Rajaraman 2004), extended that approach by providing a comprehensive hierarchical manufacturing process model with three dimensions: time, variety and aggregation, capable of representing process model for complex mechanical parts and using rule base to construct it from the product and resource data. From these experiences, the need to further capture manufacturing knowledge into a formal ontological models were recognised in DOLCE (Borgo and Leitão 2007) which focused on describing products, manufacturing process, resources and controls which describe the relations among resources and processes. Ontology MASON (Lemaignan et al. 2006) was also built in early stages to provide a taxonomy of core elements such as process, resources (machines and tools) and raw materials but lacked comprehensive treatment of relations and capabilities. PSL (Gruninger and Menzel 2003) is the development of formal language for representation of hierarchical processes in various domains. Founded on strong logical rigour and presented in Common Logic, it has been applied in a domain of manufacturing scheduling.