China
Africa
Explore chapters and articles related to this topic
Noise in digital communications systems
Published in J. Dunlop, D. G. Smith, Telecommunications Engineering, 2017
In many instances error coding is restricted to error detection rather than error correction, this is particularly true of packet transmission (see Chapter 11). When an error is detected the transmitter is requested to repeat the data, which clearly requires the provision of a return path between receiver and transmitter. In such circumstances cyclic codes are often employed and these codes are able to detect errors which occur in bursts. Cyclic codes are used to append a cyclic redundancy check (CRC) sequence to a block of information digits and are therefore a form of block code. In general the addition of c parity check digits to a block of m information digits enables any burst of c digits or less to be detected, irrespective of the length of the information block. In addition the fraction of bursts of length b > c which remain undetected by a cyclic code is 2−c if b > c + l. The length of the CRC can be altered to suit the anticipated error statistics but 16 and 32 bits are commonly used. The Ethernet packet shown in Fig. 13.1 appends a CRC of 32 bits to a block of information the length of which varies between 480 and 12112 bits, which means that if b > 33 the fraction of bursts remaining undetected is 2−32, which is a very small number.
Low Power Wide Area (LPWA) Networks for loT Applications
Published in Hongjian Sun, Chao Wang, Bashar I. Ahmad, From Internet of Things to Smart Cities, 2017
Kan. Zheng, Zhe. Yang, Xiong. Xiong, Wei. Xiang
For the purpose of validating the performance of the proposed LPWAN, several field tests are carried out in the urban environment. The AP with a wipe antenna is deployed on the roof of a 15-floor building and the devices are distributed around the AP. Through a 10-meter cable, the antenna is connected with the USRP B210 board located in the laboratory. Key parameters of our experiments are stated as follows. The operation frequency of the system is 433 MHz and the symbol rate is 200 k symbols per second. The PPDU of all data packets consists of a four-octet preamble and a 16-octet PSDU, which is spread by the Gold code with an SF of 32,768. The transmit power of the devices is set to be 15 dBm. The CRC is implemented in this system to ensure data integrity. The carrier-to-interference (C/I) is selected as the performance metric of our experiments, which is defined as the ratio of the normalized peak output of the preamble detector to the received signal power. A higher C/I implies more reliable communications. These experiments are designed to validate the LPWA system in various scenarios, e.g., the outdoor scenario, indoor scenario, underground scenario, etc. The multi-user performance of the network is tested as well. Furthermore, experimental results reveal that when the C/I value is greater than -30 dB, the AP can decode the received packets correctly.
Digital Video Interfaces
Published in Francis Rumsey, John Watkinson, Digital Interface Handbook, 2013
Francis Rumsey, John Watkinson
Surprisingly, the original SD-SDI standard had no provisions for data integrity checking. EDH is an option for SD-SDI which rectifies the omission13,14. Figure 7.47 shows an EDH equipped SDI (serial digital interface) transmission system. At the first transmitter, the data from one field is transmitted and simultaneously fed to a cyclic redundancy check (CRC) generator. The CRC calculation is a mathematical division by a polynomial and the result is the remainder. The remainder is transmitted in a special ancillary data packet sent early during the vertical interval, before any switching takes place in a router14. The first receiver has an identical CRC generator that performs a calculation on the received field. The ancillary data extractor identifies the EDH packet and demultiplexes it from the main data stream. The remainder from the ancillary packet is then compared with the locally calculated remainder. If the transmission is error free, the two values will be identical. In this case no further action results. However, if as little as one bit is in error in the data, the remainders will not match. The remainder is a 16-bit word and guarantees to detect up to 16 bits in error anywhere in the field. Greater numbers of errors are not guaranteed to be detected, but this is of little consequence as enough fields in error will be detected to indicate that there is a problem.
Overview of the challenges and solutions for 5G channel coding schemes
Published in Journal of Information and Telecommunication, 2021
Madhavsingh Indoonundon, Tulsi Pawan Fowdur
The transport block to be transmitted first goes through Downlink Shared Channel (DL-SCH) processing block in which the following operations are performed (Mathworks, 2018b): Cyclic redundancy check (CRC) codes, which help to detect errors on the receiver’s side, are attached to the data.Code block segmentation is performed to split the stream of data bits into arrays of code block segments.LDPC encoding operations are performed.Rate matching is then performed and the code block segments are concatenated into a code-word for Physical Downlink Shared Channel (PDSCH) processing.
Review of battery powered embedded systems design for mission-critical low-power applications
Published in International Journal of Electronics, 2018
Matthew Malewski, David M. J. Cowell, Steven Freear
Data corruption can be caused by various sources. These can be environmental impacts, or defects in hardware or software. The capability of detecting and correcting errors should be designed into an embedded system as it greatly increases the reliability of the system (NASA Lesson Info, 2016a). Error detection can be implemented using a simple parity bit. Upon detecting an error, the data can be re-requested. If correction is required, cyclic redundancy checks (CRCs) can be implemented. CRC is one of the most versatile error checking algorithms and is widely used throughout the electronics and IT industry (Microchip, 2008). Microcontrollers nowadays have dedicated CRC modules that allow hardware to generate and compute CRCs.
An Intelligent and Power Efficient Biomedical Sensor Node for Wireless Cardiovascular Health Monitoring
Published in IETE Journal of Research, 2022
Soumyak Chandra, Rajarshi Gupta, Saurav Ghosh, Sanjoy Mondal
|Packet Sr. No.| patient ID| compressed 40 bytes ECG data| compressed 10 bytes PPG data| 2 bytes cyclic redundancy check (CRC) check. The steps for data transfer session are given with reference to Figure 4: The Host PC directly initiates a command to the requested node (here N #3), shown in path C1.The N#3 informs MSN about this request to prevent the Host PC to initiate any further request to any other BSN till the current session is completed. This is shown in path 2.The MSN puts the N#1, N#2, N#8 and N#9 in “cyclic sleep mode” using unicast addressing, as they are not in the routing stack of N#3.ECG and PPG data are collected at N#3 and then compressed data packets are routed through the path N#3→ N#4→N#5→ N#12→N#13→N#7→N#14→N#15→Host PC (shown in dashed arrows). The algorithm steps for routing at any intermediate BSN are shown in Figure 5. At each stage, a 2-byte CRC is carried out to ascertain the data integrity.After the data transfer is successfully over, The BSN# 3 informs MSN (shown in path 5).The MSN again generates a “HELLO” message in broadcast mode to all MSNs, which puts them in “cyclic sleep mode”.