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Error control
Published in Geoff Lewis, Communications Technology Handbook, 2013
Viterbi algorithm and decoder. This maximum likelihood decoding algorithm devised by A.J. Vitberbi in 1967, together with the development of Viterbi decoder integrated circuits that make the concept transparent to the user, has done much to make convolution codes both practical and popular. As an example, a typical IC can handle raw data rates in excess of 1 Mbit/s, and using a code rate of 12 can achieve the same bit error rate as for uncoded data but with about 5 dB worse signal to noise ratio. The technique uses a search tree or trellis structure as shown in Fig. 11.4 and the decoder continually calculates the Hamming distance between received and valid code words within the constraint length. This is checked at each node of the tree and if an error path is detected, the decoder backtracks to the previous node and takes the alternative path.
Error Correction
Published in Jerry C. Whitaker, Microelectronics, 2018
For applications requiring large coding gain and very low bit error probabilities the idea of cascading two codes has been widely used and called concatenated coding. The most powerful combination in use is that of an outer Reed–Solomon code with an inner convolutional code. The decoding is done in two stages, which makes it intrinsically suboptimal, but its performance is a good approximation of the optimum decoder. Since the inner decoder produces errors clustered in bursts it is usually necessary to use a technique called interleaving to scatter such errors and ease the job of the outer decoder. Typically, the inner Viterbi decoder corrects enough errors so that a high-rate outer code can reduce the error probability to the desired level.
Viterbi Decoders: High Performance Algorithms and Architectures
Published in Keshab K. Parhi, Takao Nishitani, Digital Signal Processing for Multimedia Systems, 2018
Herbert Dawid, Heinrich Meyr, Olaf J. Joeressen
The behavior of the encoder is illustrated by drawing the state transitions of the FSM over time, as shown in Fig. 16.2. The resulting structure, the trellis diagram or just trellis, is used by the Viterbi decoder to find the most likely sequence of information symbols (indicated by the thick lines in Fig. 16.2) given the received symbols yk. In the trellis, all possible encoder states are drawn as nodes, and the possible state transitions are represented by lines connecting the nodes. Given the initial state of the encoder FSM, there exists a one-to-one correspondence of the FSM state sequence to the sequence of information symbols U = {uk.} with k ∈ {0, …, T − 1}.
Low power sleepy keeper technique based VLSI architecture of Viterbi decoder in WLANs
Published in Australian Journal of Electrical and Electronics Engineering, 2020
Kalavathi Devi Thangavel, Sakthivel Palaniappan
Although encoding with convolutional code is a straightforward practice, the complexity lies in the decoding of a convolutional code. There are quite a few types of algorithms for decoding a convolutional code. They are:Threshold decoding, Sequential decoding and Viterbi Decoding. The Viterbi algorithm comprises an encoder and a decoder. The encoder algorithm is generally straightforward and is usually implemented by dedicated hardware. In contrast, the decoder is much more complicated and consumes many more cycles. The Viterbi Algorithm, implemented in hardware, is referred to as the Viterbi decoder. The block diagram of the Viterbi decoder is shown in Figure 2. It is composed of three functional units.