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Digital Circuit Design with Very-High-Speed Integrated Circuit Hardware Description Language
Published in A. Arockia Bazil Raj, FPGA-Based Embedded System Developer's Guide, 2018
One can introduce new types by using the type declaration, which names the type and specifies its value range. The syntax is type identifier is type_definition, for example, type small_int is range 0 to 1024, type my_word_length is range 31 downto 0, subtype int_small is integer range −1024 to +1024 and subtype data_word is my_word_length range 7 downto 0. A subtype is a subset of a previously defined type. It defines a type called data_word that is a subtype of my_word_length whose range is restricted from 7 to 0. The floating-point types can be declared as type cmos_level is range 0.0 to 3.3, type pmos_level is range −5.0 to 0.0, type probability is range 0.0 to 1.0 and subtype cmos_low_V is cmos_level range 0.0 to +1.8. The physical type definition includes a units identifier as follows: type conductance is range 0 to 2E−9, units: mho; mmho = 1E−3 mho; umho = 1E−6 mho; nmho = 1E−9 mho; pmho = 1E-12 mho; end. The variables and conductance can be declared in VHDL as variable BUS_WIDTH: small_int :=24, signal DATA_BUS: my_word_length, variable VAR1: cmos_level range 0.0 to 2.5 and constant LINE_COND: conductance:= 125 umho. Notice that a space must be left before the unit name. The physical data types are not supported by the Xilinx Foundation Express synthesis program. In order to use our own types, we need to either include the type definition inside an architecture body or to declare the type in a package. An enumerated type consists of lists of character literals or identifiers. The enumerated type can be very handy when writing models at an abstract level. The syntax for an enumerated type is type type_name is (identifier list or character literal), for example, type my_3values is (‘0’, ‘1’, ‘Z’), type PC_OPER is (load, store, add, sub, div, mult, shiftl, shiftr), type hex_digit is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, 8’, ‘9’, ‘A’, ‘B’, ‘C’, ‘D’, ‘E’, ‘F’) and type state_type is (S0, S1, S2, S3). If one does not initialize the signal, the default initialization is the leftmost element of the list. Enumerated types have to be defined in the architecture body or inside a package. An example of an enumerated type that has been defined in the std_logic_1164 package is the std_ulogic type: type STD_ULOGIC is ( ‘U’, -- uninitialized ‘X’, -- forcing unknown ‘0’, -- forcing 0 ‘1’, -- forcing 1 ‘Z’, -- high impedance ‘W’, -- weak unknown ‘L’, -- weak 0 ‘H’. -- weak 1 ‘-‘); -- don't care
SysML-based compositional verification and safety analysis for safety-critical cyber-physical systems
Published in Connection Science, 2022
Jian Xie, Wenan Tan, Zhibin Yang, Shuming Li, Linquan Xing, Zhiqiu Huang
We use the metaclass “Situation” derived from the SysML standard safety extension (Biggs et al., 2019) to describe the properties of the Block, and uses the stereotype “Failure” to extend the “Situation” to indicate the possible unsafe state of the system functional component Block, as shown in Table 1. The failure-related information (e.g. the failure impact and the probability of occurrence) is presented by adding the Safety Profile. The attribute “FailureMode” describes the potential impact of the failure on the system, environment, and personnel. The related data type is the original type String of SysML. The attribute “FailureCondition” represents the severity of the impact caused by the failure. Its data type is the enumerated type “SeverityType”, and the related value is Catastrophic, Hazardous, Major, Minor, NoEffect. The attribute “Probability” represents the possibility of occurring the failure required by the system safety. Its data type is the enumerated type “ProbabilityType”, and the related values are Frequent, Probable, Remote, Extremely Remote, Extremely Improbable.