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Schedulability Analysis Based on Response Time Analysis
Published in Ivan Cibrario Bertolotti, Gabriele Manduchi, Real-Time Embedded Systems, 2017
Ivan Cibrario Bertolotti, Gabriele Manduchi
On the other side, analysis may produce a tight estimate of the worst-case execution time, but is more difficult to perform. It requires, in fact, an effective model of the processor (including pipelines, caches, memory, etc.) and sophisticated code analysis techniques. Moreover, as for testing, external factors not considered in analysis may arise in the real-world system. Most analysis techniques involve several distinct activities: Decompose the code of the task into a directed graph of basic blocks. Each basic block is a straight segment of code (without tests, loops, and other conditional statements).Consider each basic block and, by means of the processor model, determine its worst-case execution time.Collapse the graph by means of the available semantic information about the program and, possibly, additional annotations provided by either the programmer or the compiler.
Performance and Footprint at the Toolchain Level
Published in Ivan Cibrario Bertolotti, Tingting Hu, Embedded Software Development, 2017
Ivan Cibrario Bertolotti, Tingting Hu
A basic block is a sequence of statements with exactly one entry point at the beginning and one exit point at the end. To all purposes, it can therefore be considered as an atomic, indivisible unit by many optimization techniques. Accordingly, control flow graph generation scans the tree-based representation of a function, splits it into basic blocks and identifies all the directed edges that connect them.
LLVM-based stochastic error propagation analysis of manually developed software components
Published in Stein Haugen, Anne Barros, Coen van Gulijk, Trond Kongsvik, Jan Erik Vinnem, Safety and Reliability – Safe Societies in a Changing World, 2018
A. Morozov, K. Janschek, Y. Zhou
The LLVM IR code is structured into modules that contain functions as it is shown in Figure 4. The functions are decomposed into basic blocks. A basic block contains a sequence of single instructions. The conditional jumps between basic blocks form the control flow structure.
Modified LUT-based DTC of NPC 3-Level Inverter fed Sensorless IPMSM Drive with DC Link Voltage Balance
Published in IETE Technical Review, 2022
Toshi Sharma, Avik Bhattacharya
However if, , it implies that capacitor connected between positive bus and neutral point is discharging, whereas the capacitor connected between neutral and negative DC bus is charging. Hence, to maintain the neutral point voltage balance capacitor connected to positive bus is to be charged. It can be accomplished by selecting p-type voltage vectors i.e. voltage vectors from to , as mentioned in Table 2. Based on the output from the torque, flux and DC link capacitor hysteresis comparators and information of the stator flux location in stator flux plane a modified LUT is developed. The basic block diagram of the proposed switching sequence selector algorithm is shown in Figure 10. The proposed modified LUT for sector I is presented in Table 3.
Research on reducing fuzzy test sample set based on heuristic genetic algorithm
Published in Systems Science & Control Engineering, 2021
Zhihua Wang, Manman Cheng, Yongjian Wang
During the fuzzing test, each programme has its own basic code blocks, and the content found according to the address of the basic blocks is the corresponding code block. It is more convenient to obtain the address information of the basic block, so the basic block address is taken as the research object (each basic address block is equivalent to the gene in the genetic algorithm). Each sample is regarded as a set of elements with basic code block addresses (samples are equivalent to chromosomes in genetic algorithms). If there is a basic address block in the sample, it is represented by ‘1’, otherwise it is represented by ‘0’, and all the samples form a 0–1 matrix with 0 or 1 as the elements. The ‘1’ in the matrix represents the genes of the chromosome, and the set of genes in each column is equivalent to one chromosome.
Speed-Sensorless DTC of a Matrix Converter Fed Induction Motor Using an Adaptive Flux Observer
Published in IETE Journal of Research, 2021
Tabish Nazir Mir, Bhim Singh, Abdul Hamid Bhat
Moreover, it must be noted that position estimation and subsequent rotation of input voltage and output current vectors by that is reported in [10] is not required here since the entire control is done in the stationary domain. This makes the flux estimation algorithm simple to implement and consistent with the chosen frame of reference used in most DTC schemes. Figure 5 illustrates the basic block diagram of the overall control algorithm.