China
Africa
Explore chapters and articles related to this topic
Effect of Ground Plane and Strained Silicon on Nanoscale FET Devices
Published in Brajesh Kumar Kaushik, Nanoscale Devices, 2018
Saurabh Chaudhury, Avtar Singh
One more issue with the short-channel devices is the requirement for a reduced silicon body thickness. For a 32 nm technology node, the silicon body needs to be as thin as 10 nm to minimize DIBL through it. A thinner body adds to the series resistance of the source and drain, which reduces the mobility and device performance. A reduction in ion translates to reduced operating speed. To increase the mobility or the drive capability of the nanodevices, new devices techniques should be implemented. Strained silicon is an attractive method by which one can increase the device performances. Strain in strained silicon causes increased carrier mobility in the channel region. This results in an increase in the number of ions on and speed, which is otherwise not possible because of a non-scalable subthreshold slope. Strain improves both electron and hole mobility. Most of the semiconductor industries such as Intel and Texas Instruments have already started working on strained silicon-based devices [11,12]. Figure 3.9 shows that after the application of strain in the channel, the charges attain larger mobility as compared to the channel that is not under strain.
Memory Devices
Published in Chinmay K. Maiti, Introducing Technology Computer-Aided Design (TCAD), 2017
As a CMOS approaches the 22 nm node and below, to address the scaling challenges, new materials and approaches are required toward memory scaling with devices which use conventional CMOS materials. Lower operating voltages and faster switching can be achieved by using bandgap-engineered gate stacks, multiple metal floating gates, thinner oxides, and tunneling as the main programming mechanisms. Floating-gate devices are commonly used as storage elements but they may find applications as logic circuit elements within CMOS logic. To circumvent the limitations of conventional scaling, the semiconductor industry incorporated strained-silicon technology to boost the performance of devices. Since strain alters several semiconductor properties, its effect on all device parameters needs to be investigated. From measurements it was observed that DRAM retention degenerates with mechanical stress, while in nonvolatile memory (NVM), retention is improved with tensile stress. CMOS memory can be divided into two main categories, volatile memory (random access memory, or RAM) and NVM, or read-only memory (ROM). Figure 9.1 shows the various types of semiconductor memory devices.
Nanosensor Laboratory
Published in Vinod Kumar Khanna, Nanosensors, 2021
The IBM strained silicon process, called the dual stress liner, enhances the performance of both types of semiconductor transistors, called N-channel and P-channel transistors, by stretching silicon atoms in one transistor and compressing them in the other. Strained silicon is a layer of Si, in which the Si atoms have been stretched beyond their normal interatomic distance. Because of the natural tendency for atoms inside compounds to align with one another, the atoms in the silicon layer align with those in the SiGe layer, where the atoms are farther apart. Hence, the links between the silicon atoms become extended, leading to strained silicon.
Total Dose Radiation Response of Capacitance Characteristic for Nano-scale NMOS
Published in IETE Journal of Research, 2021
Chenguang Liao, Yintang Yang, Zhangming Zhu, Minru Hao
When the uniaxial strained silicon NMOSFET device is exposed to gamma rays, electron–hole pairs are generated in the oxide. Because of the existence of electric field in gate oxide layer, the electrons are quickly absorbed by the gate, and some holes will be trapped by traps, forming positive oxide trapping charge (Not) [14]. Another part of the hole acts as a trap to form hydrogen ions (protons), which are to be released by “leaping” holes through oxides or when they are trapped near the silicon/oxide interface, and they can react to form interface trap charges (Nit) [14]. The threshold voltage is affected by the above two kinds of charges, which can be obtained as follows [20]: where the total dose . , t and kg are the hole trap concentration in the oxide layer, irradiation time and the number of electron–hole pairs (EHP) generated per unit dose, respectively [14].
Influence of gamma ray radiation on two-dimensional sub-threshold current of strained Si nano NMOSFET
Published in Radiation Effects and Defects in Solids, 2019
Minru Hao, Haiwei Fu, Yan Zhang, Feng Hao, Guoxiang Chen, Huiyong Hu, Chenguang Liao, Yan Li
Ionizing radiation can cause a large amount of charge accumulation in these oxides and insulators, and resulting in device degradation and failure. In the past 30 years, the effects of total ionization doses on radiation-induced charge accumulation in oxides have been studied in detail (9). Therefore, it is of great significance to study the irradiation electrical characteristics and the irradiation hardening technology of strained silicon device (10–13). However, the sub-threshold characteristic is an important parameter for small size devices. A number of papers reported about current of the MOS device under the radiation effect (14–17), which were based on experiment but lack of mature theory. Because uniaxial strained is more suitable for manufacturing CMOS integrated circuits than biaxial strain and its cost is lower, the research on irradiation characteristics and radiation hardening technology of uniaxial strain Si Nano-Si MOSFE devices has important practical application value. The research content can be used for Nano-scale uniaxial strained Si NMOSFE. The reliability of strain integrated devices and the application of circuits provide valuable theoretical guidance and practical basis.
Scanning the Issue
Published in IETE Journal of Research, 2021
The next paper on “Total Dose Radiation Response of Capacitance Characteristic for Nano-scale NMOS,” presents the study of strained silicon technology on CMOS device performance. It provides carrier transport analysis for NMOSFET irradiated with gamma rays. An analytical model of differential capacitance of strained silicon nano NMOSFET is presented along with simulation study. The change in gate capacitance due to radiation dose and channel stress are presented from which inferences are drawn.